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| author | Kamil Rakoczy <krakoczy@antmicro.com> | 2020-06-25 14:20:47 +0200 |
|---|---|---|
| committer | Kamil Rakoczy <krakoczy@antmicro.com> | 2020-06-25 14:32:05 +0200 |
| commit | 39c39848a21dc4f4a2c3b17842d854047ba6c16f (patch) | |
| tree | e5b1f1753d2627d6af31ab70a3630cd908cb81c8 | |
| parent | 470df03f3d6731f0b784ceb4e1b05c8583b230a8 (diff) | |
| download | yosys-39c39848a21dc4f4a2c3b17842d854047ba6c16f.tar.gz yosys-39c39848a21dc4f4a2c3b17842d854047ba6c16f.tar.bz2 yosys-39c39848a21dc4f4a2c3b17842d854047ba6c16f.zip | |
Add sub-assign and and-assign tests
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| -rw-r--r-- | tests/opt/opt_expr_combined_assign.ys | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/tests/opt/opt_expr_combined_assign.ys b/tests/opt/opt_expr_combined_assign.ys index 56fbac9de..b18923c7b 100644 --- a/tests/opt/opt_expr_combined_assign.ys +++ b/tests/opt/opt_expr_combined_assign.ys @@ -47,3 +47,37 @@ equiv_opt -assert opt_expr -fine design -load postopt select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i + +design -reset +read_verilog -sv <<EOT +module opt_expr_sub_test(input [3:0] i, input [7:0] j, output [8:0] o); +wire[8:0] a = 8'b0; +initial begin + a -= i; + a -= j; +end + assign o = a; +endmodule +EOT +proc +equiv_opt -assert opt_expr -fine +design -load postopt + +select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i + +design -reset +read_verilog -sv <<EOT +module opt_expr_and_test(input [3:0] i, input [7:0] j, output [8:0] o); +wire[8:0] a = 8'b11111111; +initial begin + a &= i; + a &= j; +end + assign o = a; +endmodule +EOT +proc +equiv_opt -assert opt_expr -fine +design -load postopt + +select -assert-count 1 t:$and r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i |