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| author | Kamil Rakoczy <krakoczy@antmicro.com> | 2020-06-25 14:17:41 +0200 |
|---|---|---|
| committer | Kamil Rakoczy <krakoczy@antmicro.com> | 2020-06-25 14:19:16 +0200 |
| commit | 470df03f3d6731f0b784ceb4e1b05c8583b230a8 (patch) | |
| tree | 95fca80809f3f3d1bf217e798b0250cb9f13424f | |
| parent | 539087f417e08c56e47b8289ec65d418f7d14792 (diff) | |
| download | yosys-470df03f3d6731f0b784ceb4e1b05c8583b230a8.tar.gz yosys-470df03f3d6731f0b784ceb4e1b05c8583b230a8.tar.bz2 yosys-470df03f3d6731f0b784ceb4e1b05c8583b230a8.zip | |
Move combined assign tests to single file
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| -rw-r--r-- | tests/opt/opt_expr_combined_assign.ys | 49 | ||||
| -rw-r--r-- | tests/opt/opt_expr_or_assignment.ys | 15 | ||||
| -rw-r--r-- | tests/opt/opt_expr_plus_assignment.ys | 15 | ||||
| -rw-r--r-- | tests/opt/opt_expr_xor_assignment.ys | 15 |
4 files changed, 49 insertions, 45 deletions
diff --git a/tests/opt/opt_expr_combined_assign.ys b/tests/opt/opt_expr_combined_assign.ys new file mode 100644 index 000000000..56fbac9de --- /dev/null +++ b/tests/opt/opt_expr_combined_assign.ys @@ -0,0 +1,49 @@ +read_verilog -sv <<EOT +module opt_expr_or_test(input [3:0] i, input [7:0] j, output [8:0] o); +wire[8:0] a = 8'b0; +initial begin + a |= i; + a |= j; +end + assign o = a; +endmodule +EOT +proc +equiv_opt -assert opt_expr -fine +design -load postopt + +select -assert-count 1 t:$or r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i + +design -reset +read_verilog -sv <<EOT +module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o); +wire[8:0] a = 8'b0; +initial begin + a += i; + a += j; +end + assign o = a; +endmodule +EOT +proc +equiv_opt -assert opt_expr -fine +design -load postopt + +select -assert-count 1 t:$add r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i + +design -reset +read_verilog -sv <<EOT +module opt_expr_xor_test(input [3:0] i, input [7:0] j, output [8:0] o); +wire[8:0] a = 8'b0; +initial begin + a ^= i; + a ^= j; +end + assign o = a; +endmodule +EOT +proc +equiv_opt -assert opt_expr -fine +design -load postopt + +select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i diff --git a/tests/opt/opt_expr_or_assignment.ys b/tests/opt/opt_expr_or_assignment.ys deleted file mode 100644 index 21e08550f..000000000 --- a/tests/opt/opt_expr_or_assignment.ys +++ /dev/null @@ -1,15 +0,0 @@ -read_verilog -sv <<EOT -module opt_expr_or_test(input [3:0] i, input [7:0] j, output [8:0] o); -wire[8:0] a = 8'b0; -initial begin - a |= i; - a |= j; -end - assign o = a; -endmodule -EOT -proc -equiv_opt -assert opt_expr -fine -design -load postopt - -select -assert-count 1 t:$or r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i diff --git a/tests/opt/opt_expr_plus_assignment.ys b/tests/opt/opt_expr_plus_assignment.ys deleted file mode 100644 index 8d8ee5214..000000000 --- a/tests/opt/opt_expr_plus_assignment.ys +++ /dev/null @@ -1,15 +0,0 @@ -read_verilog -sv <<EOT -module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o); -wire[8:0] a = 8'b0; -initial begin - a += i; - a += j; -end - assign o = a; -endmodule -EOT -proc -equiv_opt -assert opt_expr -fine -design -load postopt - -select -assert-count 1 t:$add r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i diff --git a/tests/opt/opt_expr_xor_assignment.ys b/tests/opt/opt_expr_xor_assignment.ys deleted file mode 100644 index 924185e09..000000000 --- a/tests/opt/opt_expr_xor_assignment.ys +++ /dev/null @@ -1,15 +0,0 @@ -read_verilog -sv <<EOT -module opt_expr_xor_test(input [3:0] i, input [7:0] j, output [8:0] o); -wire[8:0] a = 8'b0; -initial begin - a ^= i; - a ^= j; -end - assign o = a; -endmodule -EOT -proc -equiv_opt -assert opt_expr -fine -design -load postopt - -select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i |