Merge remote-tracking branch 'origin/master' into xaig_dff

12 files changed, 81 insertions, 71 deletions

diff --git a/Makefile b/Makefile
index 2efa5e72c..16341a268 100644
--- a/Makefile
+++ b/Makefile
@@ -682,6 +682,7 @@ endif
 
 test: $(TARGETS) $(EXTRA_TARGETS)
 	+cd tests/simple && bash run-test.sh $(SEEDOPT)
+	+cd tests/simple_abc9 && bash run-test.sh $(SEEDOPT)
 	+cd tests/hana && bash run-test.sh $(SEEDOPT)
 	+cd tests/asicworld && bash run-test.sh $(SEEDOPT)
 	# +cd tests/realmath && bash run-test.sh $(SEEDOPT)
@@ -697,7 +698,6 @@ test: $(TARGETS) $(EXTRA_TARGETS)
 	+cd tests/opt && bash run-test.sh
 	+cd tests/aiger && bash run-test.sh $(ABCOPT)
 	+cd tests/arch && bash run-test.sh
-	+cd tests/simple_abc9 && bash run-test.sh $(SEEDOPT)
 	@echo ""
 	@echo "  Passed \"make test\"."
 	@echo ""
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index 734cbcf81..c53fb3113 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -127,7 +127,7 @@ bool mergeable(RTLIL::Cell *a, RTLIL::Cell *b)
 
 RTLIL::IdString decode_port_semantics(RTLIL::Cell *cell, RTLIL::IdString port_name)
 {
-	if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt), ID($div), ID($mod), ID($concat), SHIFT_OPS) && port_name == ID(B))
+	if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt), ID($div), ID($mod), ID($concat), SHIFT_OPS) && port_name == ID::B)
 		return port_name;
 
 	return "";
@@ -135,9 +135,9 @@ RTLIL::IdString decode_port_semantics(RTLIL::Cell *cell, RTLIL::IdString port_na
 
 RTLIL::SigSpec decode_port_sign(RTLIL::Cell *cell, RTLIL::IdString port_name) {
 
-	if (cell->type == ID($alu) && port_name == ID(B))
+	if (cell->type == ID($alu) && port_name == ID::B)
 		return cell->getPort(ID(BI));
-	else if (cell->type == ID($sub) && port_name == ID(B))
+	else if (cell->type == ID($sub) && port_name == ID::B)
 		return RTLIL::Const(1, 1);
 
 	return RTLIL::Const(0, 1);
@@ -173,9 +173,9 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
 	for (const auto& p : ports) {
 		auto op = p.op;
 
-		RTLIL::IdString muxed_port_name = ID(A);
-		if (decode_port(op, ID(A), &assign_map) == operand)
-			muxed_port_name = ID(B);
+		RTLIL::IdString muxed_port_name = ID::A;
+		if (decode_port(op, ID::A, &assign_map) == operand)
+			muxed_port_name = ID::B;
 
 		auto operand = decode_port(op, muxed_port_name, &assign_map);
 		if (operand.sig.size() > max_width)
@@ -204,9 +204,9 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
 		if (muxed_op.sign != muxed_operands[0].sign)
 			muxed_op = ExtSigSpec(module->Neg(NEW_ID, muxed_op.sig, muxed_op.is_signed));
 
-	RTLIL::SigSpec mux_y = mux->getPort(ID(Y));
-	RTLIL::SigSpec mux_a = mux->getPort(ID(A));
-	RTLIL::SigSpec mux_b = mux->getPort(ID(B));
+	RTLIL::SigSpec mux_y = mux->getPort(ID::Y);
+	RTLIL::SigSpec mux_a = mux->getPort(ID::A);
+	RTLIL::SigSpec mux_b = mux->getPort(ID::B);
 	RTLIL::SigSpec mux_s = mux->getPort(ID(S));
 
 	RTLIL::SigSpec shared_pmux_a = RTLIL::Const(RTLIL::State::Sx, max_width);
@@ -216,24 +216,24 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
 	int conn_width = ports[0].sig.size();
 	int conn_offset = ports[0].mux_port_offset;
 
-	shared_op->setPort(ID(Y), shared_op->getPort(ID(Y)).extract(0, conn_width));
+	shared_op->setPort(ID::Y, shared_op->getPort(ID::Y).extract(0, conn_width));
 
 	if (mux->type == ID($pmux)) {
 		shared_pmux_s = RTLIL::SigSpec();
 
 		for (const auto &p : ports) {
 			shared_pmux_s.append(mux_s[p.mux_port_id]);
-			mux_b.replace(p.mux_port_id * mux_a.size() + conn_offset, shared_op->getPort(ID(Y)));
+			mux_b.replace(p.mux_port_id * mux_a.size() + conn_offset, shared_op->getPort(ID::Y));
 		}
 	} else {
 		shared_pmux_s = RTLIL::SigSpec{mux_s, module->Not(NEW_ID, mux_s)};
-		mux_a.replace(conn_offset, shared_op->getPort(ID(Y)));
-		mux_b.replace(conn_offset, shared_op->getPort(ID(Y)));
+		mux_a.replace(conn_offset, shared_op->getPort(ID::Y));
+		mux_b.replace(conn_offset, shared_op->getPort(ID::Y));
 	}
 
-	mux->setPort(ID(A), mux_a);
-	mux->setPort(ID(B), mux_b);
-	mux->setPort(ID(Y), mux_y);
+	mux->setPort(ID::A, mux_a);
+	mux->setPort(ID::B, mux_b);
+	mux->setPort(ID::Y, mux_y);
 	mux->setPort(ID(S), mux_s);
 
 	for (const auto &op : muxed_operands)
@@ -251,11 +251,11 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
 
 	shared_op->setParam(ID(Y_WIDTH), conn_width);
 
-	if (decode_port(shared_op, ID(A), &assign_map) == operand) {
-		shared_op->setPort(ID(B), mux_to_oper);
+	if (decode_port(shared_op, ID::A, &assign_map) == operand) {
+		shared_op->setPort(ID::B, mux_to_oper);
 		shared_op->setParam(ID(B_WIDTH), max_width);
 	} else {
-		shared_op->setPort(ID(A), mux_to_oper);
+		shared_op->setPort(ID::A, mux_to_oper);
 		shared_op->setParam(ID(A_WIDTH), max_width);
 	}
 }
@@ -286,9 +286,9 @@ void check_muxed_operands(std::vector<const OpMuxConn *> &ports, const ExtSigSpe
 		auto p = *it;
 		auto op = p->op;
 
-		RTLIL::IdString muxed_port_name = ID(A);
-		if (decode_port(op, ID(A), &assign_map) == shared_operand) {
-			muxed_port_name = ID(B);
+		RTLIL::IdString muxed_port_name = ID::A;
+		if (decode_port(op, ID::A, &assign_map) == shared_operand) {
+			muxed_port_name = ID::B;
 		}
 
 		auto operand = decode_port(op, muxed_port_name, &assign_map);
@@ -315,7 +315,7 @@ ExtSigSpec find_shared_operand(const OpMuxConn* seed, std::vector<const OpMuxCon
 
 	auto op_a = seed->op;
 
-	for (RTLIL::IdString port_name : {ID(A), ID(B)}) {
+	for (RTLIL::IdString port_name : {ID::A, ID::B}) {
 		oper = decode_port(op_a, port_name, &assign_map);
 		auto operand_users = operand_to_users.at(oper);
 
@@ -355,7 +355,7 @@ dict<RTLIL::SigSpec, OpMuxConn> find_valid_op_mux_conns(RTLIL::Module *module, d
 	std::function<void(RTLIL::SigBit)> remove_outsig_from_aux_bit = [&](RTLIL::SigBit auxbit) {
 		auto aux_outsig = op_aux_to_outsig.at(auxbit);
 		auto op = outsig_to_operator.at(aux_outsig);
-		auto op_outsig = assign_map(op->getPort(ID(Y)));
+		auto op_outsig = assign_map(op->getPort(ID::Y));
 		remove_outsig(op_outsig);
 
 		for (auto aux_outbit : aux_outsig)
@@ -367,11 +367,11 @@ dict<RTLIL::SigSpec, OpMuxConn> find_valid_op_mux_conns(RTLIL::Module *module, d
 		int mux_port_size;
 
 		if (mux->type.in(ID($mux), ID($_MUX_))) {
-			mux_port_size = mux->getPort(ID(A)).size();
-			sig = RTLIL::SigSpec{mux->getPort(ID(B)), mux->getPort(ID(A))};
+			mux_port_size = mux->getPort(ID::A).size();
+			sig = RTLIL::SigSpec{mux->getPort(ID::B), mux->getPort(ID::A)};
 		} else {
-			mux_port_size = mux->getPort(ID(A)).size();
-			sig = mux->getPort(ID(B));
+			mux_port_size = mux->getPort(ID::A).size();
+			sig = mux->getPort(ID::B);
 		}
 
 		auto mux_insig = assign_map(sig);
@@ -510,12 +510,12 @@ struct OptSharePass : public Pass {
 					}
 				}
 
-				auto mux_insig = assign_map(cell->getPort(ID(Y)));
+				auto mux_insig = assign_map(cell->getPort(ID::Y));
 				outsig_to_operator[mux_insig] = cell;
 				for (auto outbit : mux_insig)
 					op_outbit_to_outsig[outbit] = mux_insig;
 
-				for (RTLIL::IdString port_name : {ID(A), ID(B)}) {
+				for (RTLIL::IdString port_name : {ID::A, ID::B}) {
 					auto op_insig = decode_port(cell, port_name, &assign_map);
 					op_insigs.push_back(op_insig);
 					operand_to_users[op_insig].insert(cell);
diff --git a/passes/pmgen/.gitignore b/passes/pmgen/.gitignore
index 0ad36ea2c..e52f3282f 100644
--- a/passes/pmgen/.gitignore
+++ b/passes/pmgen/.gitignore
@@ -1,2 +1 @@
-/ice40_dsp_pm.h
-/peepopt_pm.h
+/*_pm.h
diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc
index e766f2cf6..0242256e5 100644
--- a/passes/techmap/dff2dffe.cc
+++ b/passes/techmap/dff2dffe.cc
@@ -265,7 +265,7 @@ struct Dff2dffePass : public Pass {
 		log("\n");
 		log("    -unmap\n");
 		log("        operate in the opposite direction: replace $dffe cells with combinations\n");
-		log("        of $dff and $mux cells. the options below are ignore in unmap mode.\n");
+		log("        of $dff and $mux cells. the options below are ignored in unmap mode.\n");
 		log("\n");
 		log("    -unmap-mince N\n");
 		log("        Same as -unmap but only unmap $dffe where the clock enable port\n");
diff --git a/tests/fsm/run-test.sh b/tests/fsm/run-test.sh
index cf506470d..fbdcbf048 100755
--- a/tests/fsm/run-test.sh
+++ b/tests/fsm/run-test.sh
@@ -6,7 +6,7 @@
 set -e
 
 OPTIND=1
-count=100
+count=50
 seed=""    # default to no seed specified
 while getopts "c:S:" opt
 do
diff --git a/tests/opt/opt_rmdff.ys b/tests/opt/opt_rmdff.ys
index 081f81782..83a162f44 100644
--- a/tests/opt/opt_rmdff.ys
+++ b/tests/opt/opt_rmdff.ys
@@ -19,8 +19,8 @@ hierarchy -top equiv
 equiv_simple -undef
 equiv_status -assert
 
-design -load gold
-stat
-
-design -load gate
-stat
+#design -load gold
+#stat
+#
+#design -load gate
+#stat
diff --git a/tests/simple_abc9/.gitignore b/tests/simple_abc9/.gitignore
index 598951333..2355aea29 100644
--- a/tests/simple_abc9/.gitignore
+++ b/tests/simple_abc9/.gitignore
@@ -1,3 +1,4 @@
 *.v
+*.sv
 *.log
 *.out
diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh
index 4935d41ad..49ae23338 100755
--- a/tests/simple_abc9/run-test.sh
+++ b/tests/simple_abc9/run-test.sh
@@ -18,5 +18,6 @@ if ! which iverilog > /dev/null ; then
 fi
 
 cp ../simple/*.v .
+cp ../simple/*.sv .
 DOLLAR='?'
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4 -box ../abc.box; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'"
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-n 300 -p 'hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4 -box ../abc.box; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'"
diff --git a/tests/various/.gitignore b/tests/various/.gitignore
index 31078b298..4b286fd61 100644
--- a/tests/various/.gitignore
+++ b/tests/various/.gitignore
@@ -2,3 +2,4 @@
 /*.out
 /write_gzip.v
 /write_gzip.v.gz
+/run-test.mk
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index af23fcec8..3e90419af 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -6,7 +6,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
@@ -21,7 +21,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
@@ -52,7 +52,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 2 t:$pmux
 design -stash gate
@@ -67,7 +67,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
@@ -82,7 +82,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
@@ -97,7 +97,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
@@ -112,7 +112,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
@@ -127,7 +127,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
@@ -142,7 +142,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 7 t:$mux
 select -assert-count 0 t:$pmux
 design -stash gate
@@ -157,7 +157,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 4 t:$mux
 select -assert-count 0 t:$pmux
 design -stash gate
@@ -172,7 +172,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 3 t:$mux
 select -assert-count 0 t:$pmux
 design -stash gate
@@ -204,7 +204,7 @@ prep
 design -save gold
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 2 t:$pmux
 design -stash gate
@@ -222,7 +222,7 @@ opt -fast -mux_undef
 select -assert-count 2 t:$pmux
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
@@ -240,7 +240,7 @@ opt -fast -mux_undef
 select -assert-count 2 t:$pmux
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 2 t:$pmux
 design -stash gate
@@ -258,7 +258,7 @@ opt -fast -mux_undef
 select -assert-count 2 t:$pmux
 muxpack
 opt
-stat
+#stat
 select -assert-count 0 t:$mux
 select -assert-count 2 t:$pmux
 design -stash gate
diff --git a/tests/various/run-test.sh b/tests/various/run-test.sh
index 92b905765..ea56b70f0 100755
--- a/tests/various/run-test.sh
+++ b/tests/various/run-test.sh
@@ -1,12 +1,20 @@
 #!/usr/bin/env bash
 set -e
+{
+echo "all::"
 for x in *.ys; do
-	echo "Running $x.."
-	../../yosys -ql ${x%.ys}.log $x
+	echo "all:: run-$x"
+	echo "run-$x:"
+	echo "	@echo 'Running $x..'"
+	echo "	@../../yosys -ql ${x%.ys}.log $x"
 done
 for s in *.sh; do
 	if [ "$s" != "run-test.sh" ]; then
-		echo "Running $s.."
-		bash $s
+		echo "all:: run-$s"
+		echo "run-$s:"
+		echo "	@echo 'Running $s..'"
+		echo "	@bash $s"
 	fi
 done
+} > run-test.mk
+exec ${MAKE:-make} -f run-test.mk
diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys
index d644a88aa..0e5fe882b 100644
--- a/tests/various/shregmap.ys
+++ b/tests/various/shregmap.ys
@@ -11,7 +11,7 @@ shregmap -init
 
 opt
 
-stat
+# stat
 # show -width
 select -assert-count 1 t:$_DFF_P_
 select -assert-count 2 t:$__SHREG_DFF_P_
@@ -26,11 +26,11 @@ prep
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports -seq 5 miter
 
-design -load gold
-stat
+#design -load gold
+#stat
 
-design -load gate
-stat
+#design -load gate
+#stat
 
 ##########
 
@@ -43,9 +43,9 @@ design -save gold
 simplemap t:$dff t:$dffe
 shregmap -tech xilinx
 
-stat
+#stat
 # show -width
-write_verilog -noexpr -norename
+# write_verilog -noexpr -norename
 select -assert-count 1 t:$_DFF_P_
 select -assert-count 2 t:$__XILINX_SHREG_
 
@@ -59,8 +59,8 @@ prep
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports -seq 5 miter
 
-design -load gold
-stat
+# design -load gold
+# stat
 
-design -load gate
-stat
+# design -load gate
+# stat