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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-19 15:15:43 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-19 15:15:43 -0700 |
| commit | 526e0813427aae24b9df2eacbbb8c067bdfd5eec (patch) | |
| tree | 73a0ab6fd54626150011ce043a02f1a20de984bf | |
| parent | 45d4b33f0c2140d764a3a16b14286f6651fbbae6 (diff) | |
| download | yosys-526e0813427aae24b9df2eacbbb8c067bdfd5eec.tar.gz yosys-526e0813427aae24b9df2eacbbb8c067bdfd5eec.tar.bz2 yosys-526e0813427aae24b9df2eacbbb8c067bdfd5eec.zip | |
Add arrival times for SRL outputs
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 910d0e246..e5d9f480b 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -353,7 +353,8 @@ module RAM128X1D ( endmodule module SRL16E ( - output Q, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 + (* abc_arrival=1472 *) output Q, input A0, A1, A2, A3, CE, CLK, D ); parameter [15:0] INIT = 16'h0000; @@ -371,8 +372,9 @@ module SRL16E ( endmodule module SRLC32E ( - output Q, - output Q31, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 + (* abc_arrival=1472 *) output Q, + (* abc_arrival=1114 *) output Q31, input [4:0] A, input CE, CLK, D ); |