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| author | Miodrag Milanovic <mmicko@gmail.com> | 2021-11-10 10:50:44 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2021-11-10 10:50:44 +0100 |
| commit | 15a35f5584977605e685d2a92126a337a474ae89 (patch) | |
| tree | b268c1d3d69e44b0ce9e1dfbccf96b687a7c640e | |
| parent | 224c6f8664dc97e525b1028db9085091bfd31cd5 (diff) | |
| download | yosys-15a35f5584977605e685d2a92126a337a474ae89.tar.gz yosys-15a35f5584977605e685d2a92126a337a474ae89.tar.bz2 yosys-15a35f5584977605e685d2a92126a337a474ae89.zip | |
No need to alocate more memory than used
| -rw-r--r-- | frontends/verific/verific.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 5a75b52af..47020f105 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1143,7 +1143,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se module->memories[memory->name] = memory; int number_of_bits = net->Size(); - number_of_bits = 1 << ceil_log2(number_of_bits); int bits_in_word = number_of_bits; FOREACH_PORTREF_OF_NET(net, si, pr) { if (pr->GetInst()->Type() == OPER_READ_PORT) { |