Commit message (Collapse) | Author | Age | Files | Lines | ||
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* | ice40: Improve the is_sb_pll40_XXX predicates collection | Sylvain Munaut | 2018-11-19 | 1 | -1/+13 | |
| | | | | | | | | | - Add a test for dual output PLL variant - Make them handle the packet version of the cell This will become useful for various tests during PLL rework Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
* | ice40: Fix PLLTYPE for SB_PLL40_2F_PAD | Sylvain Munaut | 2018-11-19 | 1 | -1/+1 | |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
* | ice40/pll: Add proper support for PLLOUT_SELECT_xxx attributes | Sylvain Munaut | 2018-11-19 | 1 | -0/+18 | |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
* | ice40: Make PLL default FEEDBACK_MODE to SIMPLE | Sylvain Munaut | 2018-11-19 | 1 | -1/+1 | |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
* | ice40: Minor fix in predicate checking for logic port | Sylvain Munaut | 2018-11-19 | 1 | -2/+3 | |
| | | | | | | | - is_sb_pll40 covers all the PLL types - Use helper to test for gbuf Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
* | ice40/pack: Stop looking for BEL when we have one during PLL placement | Sylvain Munaut | 2018-11-19 | 1 | -0/+1 | |
| | | | | | | | Ideally we should first process all the PLL that are constrained somehow (either explicitely or because they are PAD) and then free place the rest. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
* | ice40/pack: Allow PLL to be constrained via 'BEL' attributes | Sylvain Munaut | 2018-11-19 | 1 | -0/+10 | |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
* | ice40/pack: Make sure we don't use a LOCKED bel when placing PLL | Sylvain Munaut | 2018-11-19 | 1 | -0/+2 | |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
* | ice40/arch: Add helper to check if a BEL is LOCKED or not | Sylvain Munaut | 2018-11-19 | 2 | -0/+21 | |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
* | ice40/chipdb: Fix LOCKED keyword support to include all packages | Sylvain Munaut | 2018-11-19 | 1 | -1/+2 | |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
* | ice40/bitstream: Handle IoCtrl.IE_ polarity when configuring unused SB_IO | Sylvain Munaut | 2018-11-19 | 1 | -2/+7 | |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
* | ice40: Add warning if an instanciated SB_IO has its PACKAGE_PIN used elsewhere | Sylvain Munaut | 2018-11-16 | 1 | -0/+5 | |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
* | ice40/bitstream: Convert to UNIX line endings | Sylvain Munaut | 2018-11-16 | 1 | -1043/+1043 | |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
* | clangformat | David Shah | 2018-11-16 | 1 | -2/+2 | |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
* | ice40: Remove unnecessary RAM assertion | David Shah | 2018-11-16 | 1 | -1/+0 | |
| | | | | | | Fixes #121 Signed-off-by: David Shah <dave@ds0.me> | |||||
* | Merge remote-tracking branch 'origin/master' into timingapi | Eddie Hung | 2018-11-13 | 2 | -4/+5 | |
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| * | [ice40] getBudgetOverride() to use constrained Z not placed Z | Eddie Hung | 2018-11-13 | 2 | -4/+5 | |
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* | | Merge remote-tracking branch 'origin/master' into timingapi | Eddie Hung | 2018-11-13 | 3 | -18/+41 | |
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| * | Merge pull request #107 from YosysHQ/router_improve | Eddie Hung | 2018-11-13 | 2 | -17/+40 | |
| |\ | | | | | | | Major rewrite of "router1" | |||||
| | * | Various router1 fixes, Add BelId/WireId/PipId::operator<() | Clifford Wolf | 2018-11-13 | 1 | -0/+3 | |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | clangformat | Clifford Wolf | 2018-11-11 | 1 | -4/+1 | |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Add getConflictingWireWire() arch API, streamline getConflictingXY semantic | Clifford Wolf | 2018-11-11 | 1 | -14/+29 | |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Add getConflictingPipWire() arch API, router1 improvements | Clifford Wolf | 2018-11-11 | 1 | -9/+17 | |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Mark getArchOptions as override in derived classes | Pedro Vanzella | 2018-11-13 | 1 | -1/+1 | |
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* | | | timing: Add support for clock constraints | David Shah | 2018-11-12 | 2 | -0/+12 | |
| | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
* | | | archapi: Add getDelayFromNS to improve timing algorithm portability | David Shah | 2018-11-12 | 1 | -0/+6 | |
| | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
* | | | timing: Fix handling of clock inputs | David Shah | 2018-11-12 | 1 | -2/+2 | |
| | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
* | | | Working on multi-clock analysis | David Shah | 2018-11-12 | 1 | -6/+4 | |
| | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
* | | | timing: iCE40 Arch API changes for clocking info | David Shah | 2018-11-12 | 3 | -21/+68 | |
|/ / | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
* | | ice40: Don't set colbuf bits for 384 | David Shah | 2018-11-11 | 1 | -0/+2 | |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
* | | Merge pull request #93 from YosysHQ/gui_changes | Miodrag Milanović | 2018-11-10 | 1 | -2/+2 | |
|\ \ | |/ |/| | Gui changes | |||||
| * | fix grid dimensions for ice40 | Miodrag Milanovic | 2018-10-27 | 1 | -2/+2 | |
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* | | ice40: Fix SPRAM and IO globals | David Shah | 2018-11-04 | 1 | -0/+4 | |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
* | | ice40: Fix PLL DYNAMICDELAY | David Shah | 2018-10-27 | 1 | -1/+2 | |
|/ | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
* | ups, uncomment | Miodrag Milanovic | 2018-10-27 | 1 | -2/+2 | |
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* | Fixed pip graphics | Miodrag Milanovic | 2018-10-27 | 1 | -4/+4 | |
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* | Merge pull request #88 from YosysHQ/issue72 | Eddie Hung | 2018-10-11 | 1 | -6/+13 | |
|\ | | | | | Resolve issue #72 | |||||
| * | [ice40] TimingPortClass of LC.O ports without any inputs now TMG_IGNORE | Eddie Hung | 2018-09-15 | 1 | -6/+13 | |
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* | | Add info message for promoted global nets | Clifford Wolf | 2018-10-03 | 1 | -0/+2 | |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | | ice40: Add error for bad PACKAGE_PIN connections | David Shah | 2018-10-03 | 1 | -2/+13 | |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
* | | Refactor chain finder to its own file | David Shah | 2018-09-30 | 1 | -39/+1 | |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
* | | clangformat | David Shah | 2018-09-30 | 8 | -28/+34 | |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
* | | Merge pull request #79 from YosysHQ/ice40lvds | Clifford Wolf | 2018-09-25 | 8 | -13/+88 | |
|\ \ | | | | | | | ice40: Adding LVDS input support | |||||
| * | | ice40: LVDS input bitstream support | David Shah | 2018-09-24 | 1 | -4/+48 | |
| | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | ice40: Tristate IO support fixes | David Shah | 2018-09-24 | 3 | -6/+10 | |
| | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | ice40: Validity check for LVDS IO | David Shah | 2018-09-24 | 4 | -0/+29 | |
| | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | ice40: Remove obsolete belType member | David Shah | 2018-09-24 | 3 | -3/+1 | |
| |/ | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
* | | Merge pull request #76 from YosysHQ/plloutglobal_fix | Clifford Wolf | 2018-09-25 | 2 | -2/+38 | |
|\ \ | | | | | | | Add needed PLLOUTGLOBAL ports and mapped it | |||||
| * | | Added required checks for PLL and fixed messages eol | Miodrag Milanovic | 2018-09-19 | 1 | -3/+31 | |
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| * | | Add needed PLLOUTGLOBAL ports and mapped it properly | Miodrag Milanovic | 2018-09-12 | 2 | -0/+8 | |
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