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author | David Shah <dave@ds0.me> | 2018-11-12 13:42:25 +0000 |
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committer | David Shah <dave@ds0.me> | 2018-11-12 14:03:58 +0000 |
commit | fc5e6bec9ab8bf2c25b2b943de4013daf727dfb8 (patch) | |
tree | 1f3c4171cb20e3ec8123ceef576c383fa0034d24 /ice40 | |
parent | 11579a1046640a21b79aa6a1f579d3464267d0a1 (diff) | |
download | nextpnr-fc5e6bec9ab8bf2c25b2b943de4013daf727dfb8.tar.gz nextpnr-fc5e6bec9ab8bf2c25b2b943de4013daf727dfb8.tar.bz2 nextpnr-fc5e6bec9ab8bf2c25b2b943de4013daf727dfb8.zip |
timing: Add support for clock constraints
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'ice40')
-rw-r--r-- | ice40/arch_pybindings.cc | 4 | ||||
-rw-r--r-- | ice40/pack.cc | 8 |
2 files changed, 12 insertions, 0 deletions
diff --git a/ice40/arch_pybindings.cc b/ice40/arch_pybindings.cc index f1639ba6..3fafb1f6 100644 --- a/ice40/arch_pybindings.cc +++ b/ice40/arch_pybindings.cc @@ -140,6 +140,10 @@ void arch_wrap_python() "cells"); readonly_wrapper<Context, decltype(&Context::nets), &Context::nets, wrap_context<NetMap &>>::def_wrap(ctx_cls, "nets"); + + fn_wrapper_2a_v<Context, decltype(&Context::addClock), &Context::addClock, conv_from_str<IdString>, + pass_through<float>>::def_wrap(ctx_cls, "addClock"); + WRAP_RANGE(Bel, conv_to_str<BelId>); WRAP_RANGE(Wire, conv_to_str<WireId>); WRAP_RANGE(AllPip, conv_to_str<PipId>); diff --git a/ice40/pack.cc b/ice40/pack.cc index b9360b74..7a27d505 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -490,6 +490,14 @@ static void insert_global(Context *ctx, NetInfo *net, bool is_reset, bool is_cen } } net->users = keep_users; + + if (net->clkconstr) { + glbnet->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint()); + glbnet->clkconstr->low = net->clkconstr->low; + glbnet->clkconstr->high = net->clkconstr->high; + glbnet->clkconstr->period = net->clkconstr->period; + } + ctx->nets[glbnet->name] = std::move(glbnet); ctx->cells[gb->name] = std::move(gb); } |