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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2018-10-11 02:54:19 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-10-11 02:54:19 -0700 |
| commit | 96efe48847dbf7f25f97b6059dacacd33fde4bec (patch) | |
| tree | 58013ebcf2646254d5278bc823d97d25566b829a /ice40 | |
| parent | 22973527727a3747349f2d6f234f20fd459f05c3 (diff) | |
| parent | 8749327f1efec85eed8b9b1d3cf45592533b42fc (diff) | |
| download | nextpnr-96efe48847dbf7f25f97b6059dacacd33fde4bec.tar.gz nextpnr-96efe48847dbf7f25f97b6059dacacd33fde4bec.tar.bz2 nextpnr-96efe48847dbf7f25f97b6059dacacd33fde4bec.zip | |
Merge pull request #88 from YosysHQ/issue72
Resolve issue #72
Diffstat (limited to 'ice40')
| -rw-r--r-- | ice40/arch.cc | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/ice40/arch.cc b/ice40/arch.cc index f008b617..eb26ae5a 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -865,15 +865,22 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id return TMG_COMB_INPUT; if (port == id_COUT || port == id_LO) return TMG_COMB_OUTPUT; - if (cell->lcInfo.dffEnable) { - clockPort = id_CLK; - if (port == id_O) + if (port == id_O) { + // LCs with no inputs are constant drivers + if (cell->lcInfo.inputCount == 0) + return TMG_IGNORE; + if (cell->lcInfo.dffEnable) { + clockPort = id_CLK; return TMG_REGISTER_OUTPUT; + } else - return TMG_REGISTER_INPUT; - } else { - if (port == id_O) return TMG_COMB_OUTPUT; + } + else { + if (cell->lcInfo.dffEnable) { + clockPort = id_CLK; + return TMG_REGISTER_INPUT; + } else return TMG_COMB_INPUT; } |