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* Correct Not Equal operator implementation in ice40Tyler2022-10-171-1/+1
* ice40: Fix handling of carry out route-thru via 25,14gatecat2022-09-261-15/+21
* ice40: implement checkPipAvailForNetgatecat2022-09-201-0/+10
* ice40: Fix UltraPlus BRAM clock polaritygatecat2022-09-141-3/+7
* Use CMake's Python3 rather than PythonInterp in subdirsAdam Sampson2022-08-211-2/+2
* refactor: Use IdString::in instead of || chainsgatecat2022-08-106-42/+35
* refactor: id(stringf(...)) to new idf(...) helpergatecat2022-08-101-2/+2
* ice40: Fix accidental creation of empty portsgatecat2022-06-251-9/+9
* ice40: Fix propagation of constraints through SB_GBgatecat2022-05-081-7/+24
* ice40: Avoid chain finder from mixing up chains by only allowing I3 chaining ...gatecat2022-04-111-34/+45
* ci: Restructure and move entirely to GH actions from Cirrusgatecat2022-04-081-1/+1
* ice40: Fix wirenames containing / which is the list separatorgatecat2022-03-301-1/+1
* ice40: Merge driving LUT<=2s into carry-only LCsgatecat2022-03-293-3/+90
* ice40: Improve error reporting for PLL conflictsgatecat2022-03-251-7/+32
* clangformatgatecat2022-03-171-1/+2
* ice40: fix crash when packing LUTs with no outputStefan Riesenberger2022-03-141-24/+27
* Switch to potentially-sparse net users arraygatecat2022-02-274-92/+54
* refactor: New member functions to replace design_utilsgatecat2022-02-183-47/+50
* refactor: Use constids instead of id("..")gatecat2022-02-1610-660/+798
* refactor: Use cell member functions to add portsgatecat2022-02-161-169/+162
* refactor: New NetInfo and CellInfo constructorsgatecat2022-02-164-52/+26
* Merge pull request #873 from YosysHQ/gatecat/ice40-carry-lutgatecat2022-01-161-0/+2
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| * ice40: Pack LUT at start of carry chain if there is 1 candidategatecat2021-12-141-0/+2
* | archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-192-6/+6
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* ice40: Use default value when IP is missing BUS_ADDR74 parametergatecat2021-07-201-3/+4
* ice40: Fix order of values in errorgatecat2021-07-101-1/+1
* Fixing old emails and names in copyrightsgatecat2021-06-1226-44/+44
* Remove redundant code after hashlib movegatecat2021-06-021-46/+0
* Use hashlib in most remaining codegatecat2021-06-021-2/+2
* Using hashlib in archesgatecat2021-06-026-22/+21
* Use hashlib in routersgatecat2021-06-021-1/+1
* Use hashlib for core netlist structuresgatecat2021-06-024-39/+42
* Add hash() member functionsgatecat2021-06-021-0/+6
* Add default base implementation of cluster APIgatecat2021-05-062-2/+6
* Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-152-8/+20
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-194-72/+42
* Remove isValidBelForCellgatecat2021-02-163-123/+94
* Add getBelHidden and add some missing "override" statements.Keith Rothman2021-02-111-1/+1
* Add BaseArchRanges for default ArchRanges typesgatecat2021-02-091-16/+1
* Merge pull request #568 from YosysHQ/dave/arch-overridegatecat2021-02-084-184/+117
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| * Use 'T' postfix to disambiguate LHS and RHS of usingD. Shah2021-02-081-21/+21
| * Add archArgs and archArgsToId to Arch APID. Shah2021-02-051-2/+3
| * ice40: Switch to BaseArchD. Shah2021-02-054-182/+114
* | Use RelSlice::ssize instead of cast-to-int throughoutD. Shah2021-02-081-3/+3
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* Mark IdString and IdStringList single argument constructors explicit.Keith Rothman2021-02-043-6/+6
* ice40: Use snake case for arch-specific functionsD. Shah2021-02-037-50/+50
* ice40: Implement IdStringList for all arch object namesD. Shah2021-02-025-57/+88
* refactor: Replace getXName().c_str(ctx) with ctx->nameOfXD. Shah2021-02-022-6/+5
* arch: Add getNameDelimiter API for string listsD. Shah2021-02-021-0/+1
* Run "make clangformat".Keith Rothman2021-02-024-28/+21
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