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ice40
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chipdb.py
Commit message (
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Author
Age
Files
Lines
*
ice40: Fix SPRAM and other primitives in corners other than (0, 0)
David Shah
2018-07-24
1
-1
/
+1
*
Add Context::archcheck() and "nextpnr-ice40 --test"
Clifford Wolf
2018-07-23
1
-40
/
+54
*
Bugfix in iCE40 chipdb.py
Clifford Wolf
2018-07-23
1
-3
/
+0
*
Add Arch::getBelPinType() and Arch::getWireBelPins() in iCE40 arch
Clifford Wolf
2018-07-22
1
-2
/
+27
*
ice40: Add virtual padin wires for intoscs and GB_IOs
David Shah
2018-07-19
1
-1
/
+14
*
ice40: Adding data for extra cell configuration
David Shah
2018-07-19
1
-3
/
+22
*
Remove pip names from ice40 chip db to safe memory
Clifford Wolf
2018-07-15
1
-1
/
+1
*
Add iCE40 Pip gfx
Clifford Wolf
2018-07-15
1
-6
/
+24
*
Fix ice40 gfx wire indices
Clifford Wolf
2018-07-13
1
-1
/
+1
*
Updates from clang-format
Clifford Wolf
2018-07-12
1
-1
/
+3
*
Fix ice40 wire segments in lutff complex
Clifford Wolf
2018-07-12
1
-2
/
+2
*
Improve iCE40 wire database and gfx
Clifford Wolf
2018-07-12
1
-1
/
+34
*
Deterministic chipdb blobs
Clifford Wolf
2018-07-11
1
-2
/
+2
*
Add opetion to defie ICEBOX_ROOT, fix compile on other location
Miodrag Milanovic
2018-07-03
1
-1
/
+2
*
Make chibdb.py able to generate pure binary output
Miodrag Milanovic
2018-07-03
1
-5
/
+27
*
Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr
David Shah
2018-06-22
1
-1
/
+1
|
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*
Merge branch 'q3k/gl' into 'master'
Serge Bazanski
2018-06-22
1
-1
/
+1
|
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*
Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/gl
Sergiusz Bazanski
2018-06-22
1
-4
/
+66
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*
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chipdb.py style fix
Sergiusz Bazanski
2018-06-20
1
-1
/
+1
*
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ice40: Adding extra cell wires to database; SB_WARMBOOT working
David Shah
2018-06-22
1
-0
/
+47
|
/
/
/
*
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/
ice40: Preparations for extra cells support
David Shah
2018-06-22
1
-0
/
+12
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*
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ice40: Add UltraPlus tiles to database
David Shah
2018-06-22
1
-4
/
+66
|
/
*
Improve --tmfuzz mode and iCE40 delay estimator
Clifford Wolf
2018-06-20
1
-4
/
+4
*
Fix chipdb UltraPlus wires
David Shah
2018-06-20
1
-1
/
+1
*
Add better iCE40 delay estimates
Clifford Wolf
2018-06-20
1
-5
/
+113
*
Refactore ice40 chipdb to use a super-large C-string as output format
Clifford Wolf
2018-06-17
1
-18
/
+76
*
Minor chipdb.py improvement
Clifford Wolf
2018-06-17
1
-2
/
+17
*
Move top-level ChipInfoPOD into ice40 chipdb blob
Clifford Wolf
2018-06-17
1
-19
/
+32
*
Move PackageInfoPOD to ice40 chipdb blob
Clifford Wolf
2018-06-17
1
-6
/
+8
*
Move TileType array to ice40 chipdb blob
Clifford Wolf
2018-06-17
1
-6
/
+13
*
Move BitstreamInfoPOD to ice40 chipdb blob
Clifford Wolf
2018-06-17
1
-8
/
+14
*
Move IerenInfoPOD to ice40 chipdb blob
Clifford Wolf
2018-06-17
1
-12
/
+11
*
Move TileInfoPOD to chipdb blob
Clifford Wolf
2018-06-17
1
-6
/
+14
*
Move SwitchInfoPOD to chipdb blob
Clifford Wolf
2018-06-17
1
-14
/
+24
*
Move PipInfoPOD into ChipDB binary blob
Clifford Wolf
2018-06-17
1
-6
/
+28
*
Move WireInfoPOD into ChipDB binary blob
Clifford Wolf
2018-06-17
1
-26
/
+48
*
Minor refactoring of BinaryBlobAssembler, fix alignments
Clifford Wolf
2018-06-17
1
-67
/
+123
*
Progress with chipdb refactoring
Clifford Wolf
2018-06-16
1
-10
/
+22
*
Progress with chipdb refactoring
Clifford Wolf
2018-06-16
1
-39
/
+34
*
Progress with chipdb refactoring
Clifford Wolf
2018-06-16
1
-9
/
+150
*
Some refactoring of Chip API (prep for chipdb refactoring)
Clifford Wolf
2018-06-16
1
-1
/
+1
*
Drastically reduce number of linker symbols in chipdb
Clifford Wolf
2018-06-13
1
-18
/
+40
*
Add missing iCE40 global buffer bels
Clifford Wolf
2018-06-13
1
-0
/
+18
*
Add hierarchy to bel/wire/pip names
Clifford Wolf
2018-06-13
1
-6
/
+6
*
ice40: Update examples to use packer/pcf
David Shah
2018-06-13
1
-2
/
+3
*
ice40: Add package pins to database
David Shah
2018-06-13
1
-2
/
+36
*
Add nextpnr namespace
Clifford Wolf
2018-06-12
1
-1
/
+8
*
Add "nextpnr.h"
Clifford Wolf
2018-06-11
1
-1
/
+1
*
Improving 5k support
David Shah
2018-06-10
1
-2
/
+11
*
Fix iCE40 routing graph
Clifford Wolf
2018-06-10
1
-22
/
+1
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