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* gowin: add a common mechanism for placing portsYRabbit2023-04-201-0/+2
| | | | | | | If the port is in a different cell than the primitive, then use the alias mechanism. Considerably compact code for OSC as an example. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Remove inherited code for ODDR(c)YRabbit2023-04-141-1/+0
| | | | | | | Implement ODDR(c) as part of IOLOGIC and remove all old code associated with those primitives. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: implement IDES16 and OSER16 primitivesYRabbit2023-04-121-1/+5
| | | | | | | | | These are very cumbersome primitives that take up two cells and consequently 4 IOLOGIC bels. The primitives are implemented for the chips that contain them and are supported by apicula GW1NSR-4C, GW1NR-9 and GW1NR-9C. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add support for OSER primitivesYRabbit2023-03-231-10/+19
| | | | | | | | | | | | | | | | * placement of OSER4, OVIDEO, OSER8 and SER10 primitives is supported; * primitives are implemented for the GW1N-1, GW1NZ-1, GW1NSR-4C, GW1NR-9, GW1NR-9C chips; * the initial support for special HCLK clock wires is implemented to the extent necessary for OSER primitives to function; * output to both regular IO and TLVDS_OBUF is supported; * tricks required for IOLOGIC to work on one side of the -9 and -9C chips are taken into account; * various edits, such as using idf() instead of the local buffer. Compatible with old apicula bases. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Proper use of the C++ mechanismsYRabbit2023-01-301-9/+7
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add PLL support for the GW1NR-9 chipYRabbit2023-01-301-0/+9
| | | | | | | | | And also unified the fixing of PLL to bels: the point is that PLL being at a certain location has the possibility to use a direct implicit wire to the clock source, but once we decide to use this direct wire, the PLL can no longer be moved. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add PLL support for the GW1NR-9C chipYRabbit2023-01-261-1/+1
| | | | | | | | | | | | | | | | | | | | This chip is used in the Tangnano9k board. * all parameters of the rPLL primitive are supported; * all PLL outputs are treated as clock sources and optimized routing is applied to them; * primitive rPLL on different chips has a completely different structure: for example in GW1N-1 it takes two cells, and in GW1NR-9C as many as four, despite this unification was carried out and different chips are processed by the same functions, but this led to the fact that you can not use the PLL chip GW1N-1 with the old apicula bases - will issue a warning and refuse to encode primitive. In other cases compatibility is supported. * Cosmetic change: the usage report shows the rPLL names without any service bels. * I use ctx->idf() on occasion, it's not a total redesign. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add a PLL primitive for the GW1NS-4 seriesYRabbit2023-01-181-1/+6
| | | | | | | | | | * both instances of the new PLLVR type are supported; * primitive placement is optimized for the use of dedicated PLL clock pins; * all 4 outputs of each primitive can use the clock nets (only 5 lines in total at the same time so far). Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: improve clock wire routingYRabbit2022-12-301-0/+1
| | | | | | | | | | | | | | The dedicated router for clock wires now understands not only the IO pins but also the rPLL outputs as clock sources. This simple router sets an optimal route, so it is now the default router. It can be disabled with the --disable-globals command line flag if desired, but this is not recommended due to possible clock skew. Still for GW1N-4C there is no good router for clock wires as there external quartz resonator is connected via PLL. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #1059 from YosysHQ/gatecat/validity-errorsmyrtle2022-12-071-1/+1
|\ | | | | Add new option for verbose validity errors, use for ice40
| * api: add explain_invalid option to isBelLocationValidgatecat2022-12-071-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #1058 from YosysHQ/gatecat/bounds-refactormyrtle2022-12-071-1/+1
|\| | | | | refactor: rename ArcBounds -> BoundingBox and use this in HeAP
| * refactor: ArcBounds -> BoundingBoxgatecat2022-12-071-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | gowin: add PLL pins processingYRabbit2022-12-041-0/+4
|/ | | | | | | | | | | Uses the information of the special input pins for the PLL in the current chip. If such pins are involved, no routing is performed and information about the use of implicit wires is passed to the packer. The RESET and RESET_P inputs are now also disabled if they are connected to VSS/VCC. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add information about pin configurationsYRabbit2022-11-251-2/+9
| | | | | | | Includes information on additional pin functions such as RPLL_C_IN, GCLKC_3, SCLK and others. This allows a decision to be made about special network routing of such pins Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add initial PLL supportYRabbit2022-11-101-1/+3
| | | | | | | | | | | The rPLL primitive for the simplest chip (GW1N-1) in the family is processed. All parameters of the primitive are passed on to gowin_pack, and general-purpose wires are used for routing outputs of the primitive. Compatible with older versions of apicula, but in this case will refuse to place the new primitive. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Remove incomprehensible names of the muxesYRabbit2022-07-191-1/+1
| | | | | | | | | | | | There is no need to multiply item names, it is a rudiment of my very first addition to nextpnr. Fully compatible with older versions of Apicula. Note: the cosmetic changes in lines with RAM are not my initiative, but the result of applying clang-format. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Remove unnecessary functionsYRabbit2022-07-051-5/+1
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge branch 'master' into clock-wipYRabbit2022-07-051-0/+1
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| * Merge branch 'master' into shadowramPepijn de Vos2022-07-021-1/+9
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| * | lutram actually PnRsPepijn de Vos2022-06-061-1/+0
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| * | WIP shadowramPepijn de Vos2022-06-051-0/+2
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* | | gowin: Let the placer know about global networksYRabbit2022-07-041-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor in order to detect networks that will be routed in a special mode earlier. This makes it possible to mark the source of such networks as a global buffer, thereby removing their influence on element placement. In addition, timing classes are set for some cells. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | | gowin: add a separate router for the clocksYRabbit2022-06-231-0/+1
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A simple router that takes advantage of the fact that in each cell with DFFs their CLK inputs can directly connect to the global clock network. Networks with a large number of such sinks are sought and then each network is assigned to the available independent global clock networks. There are limited possibilities for routing mixed networks, that is, when the sinks are not only CLKs: in this case an attempt is made to use wires such as SN10/20 and EW10/20, that is, one short transition can be added between the global clock network and the sink. * At this time, networks with a source other than the I/O pin are not supported. This is typical for Tangnano4k and runber boards. * Router is disabled by default, you need to specify option --enable-globals to activate * No new chip bases are required. This may change in the distant future. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | gowin: Add support for long wiresYRabbit2022-05-271-1/+9
|/ | | | | | | | | | | | | | | | | | | | | | Gowin chips have a highly sophisticated system of long wires that are wired to each cell and allow the clock or logic to spread quickly. This commit implements some of the capabilities of the long wire system for quadrants, leaving out the fine-tuning of them for each column. To make use of the long wire system, the specified wire is cut at the driver and a special cell is placed between the driver and the rest of the wire. * VCC and GND can not use long wires because they are in every cell and there is no point in using a net * Long wire numbers can be specified manually or assigned automatically. * The route from the driver to the port of the new cell can be quite long, this will have to be solved somehow. * It might make sense to add a mechanism for automatically finding candidates for long wires. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: handle the GW1N-9 feature.YRabbit2022-04-031-0/+2
| | | | | | | | This chip has a different default state for one type of I/O buffer --- you have to explicitly switch it to the normal state by feeding VCC/VSS to certain inputs. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Fix z-index of oscillatorTim Pambor2022-03-301-1/+2
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* gowin: Consider the peculiarity of GW1BR-9CYRabbit2022-03-261-0/+3
| | | | | | | The GW1NR-9C chip ODDR implementation differs from all other supported chips by two suspicious inputs. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add support for ODDR primitiveYRabbit2022-03-151-4/+13
| | | | | | | | | Compatible with older versions of apicula bases. Also small fixes and as the number of virtual Bels grows it is necessary to assign them Z coordinate in a centralized way to avoid conflicts and for this purpose introduced the BelZ enum. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* refactor: Use constids instead of id("..")gatecat2022-02-161-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* gowin: Add GUI.YRabbit2022-01-291-8/+21
| | | | | | | | | | | | | | | * Items such as LUT, DFF, MUX, ALU, IOB are displayed; * Local wires, 1-2-4-8 wires are displayed; * The clock spines, taps and branches are displayed with some caveats. For now, you can not create a project in the GUI because of possible conflict with another PR (about GW1NR-9C support), but you can specify the board in the command line and load .JSON and .CST in the GUI. Although ALUs are displayed, but the CIN and COUT wires are not. This is still an unsolved problem. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Initializing the grid dimensionsYRabbit2021-12-261-1/+1
| | | | | | | gridDimX and gridDimY are not initialized explicitly, which leads to effects when the design is reloaded, say, from the GUI. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-191-1/+1
| | | | | | | | | | | | This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me>
* gowin: Check the chipdb versionYRabbit2021-11-071-0/+2
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Use speed from chip base.YRabbit2021-11-051-2/+1
| | | | | | | Another simplification of the input regular expression, now the speed is taken from the base. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add partnumbers and packages to the chipdbYRabbit2021-11-041-1/+9
| | | | | | | | | | Instead of parsing the partnumber with a regular expression, a simple table is used. This is done because the structure of the partnumber changes as new features appear (e.g., ES instead of C6/I5) This commit does not yet disable the very first regular expression check. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add support for wide LUTs.YRabbit2021-10-071-0/+3
| | | | | | | | | * A hardwired MUX within each logical cell is used. * The delay is equal 0. * No user placement constraints. * The output route contains dummy PIPs. They are ignored by gowin_pack, but it may be worth removing them. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add constraints on primitive placement.YRabbit2021-08-311-0/+3
| | | | | | | | | | Added support for the INS_LOC instruction in the constraints file (.CST), which is used to specify object placement. Expanded treatment of IO_LOC/IO_PORT constraints, which now can be applied to both ports and IO buffers. Port constraints have priority. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Fixing old emails and names in copyrightsgatecat2021-06-121-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Using hashlib in archesgatecat2021-06-021-25/+12
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-151-4/+15
| | | | | | | | | | | | | | | | | | | "nextpnr.h" is no longer the god header. Important improvements: - Functions in log.h can be used without including BaseCtx/Arch/Context. This means that log_X functions can be called without included "nextpnr.h" - NPNR_ASSERT can be used without including "nextpnr.h" by including "nextpnr_assertions.h". This allows NPNR_ASSERT to be used safely in any header file. - Types defined in "archdefs.h" are now available without including BaseCtx/Arch/Context. This means that utility classes that will be used inside of BaseCtx/Arch/Context can be defined safely in a self-contained header. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix compiler warnings introduced by -Wextragatecat2021-02-251-8/+8
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Change CellInfo in getBelPinsForCellPin to be const.Keith Rothman2021-02-231-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-19/+11
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* gowin: Use base bel bucket/cell type methodsgatecat2021-02-171-5/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Remove isValidBelForCellgatecat2021-02-161-1/+0
| | | | | | | | | | | | | | | | | This Arch API dates from when we were first working out how to implement placement validity checking, and in practice is little used by the core parts of placer1/HeAP and the Arch implementation involves a lot of duplication with isBelLocationValid. In the short term; placement validity checking is better served by the combination of checkBelAvail and isValidBelForCellType before placement; followed by isBelLocationValid after placement (potentially after moving/swapping multiple cells). Longer term, removing this API makes things a bit cleaner for a new validity checking API. Signed-off-by: gatecat <gatecat@ds0.me>
* Add getBelPinsForCellPin to Arch APIgatecat2021-02-101-0/+2
| | | | | | | | | | | | This is a basic implementation, without considering "M of N" arrangements (e.g. for LUT permuation where you only want to route to 1 out of 4/6 sinks) or using a type other than IdString to identify bel pins. But this is also enough to start working out where in nextpnr will break due to removing the 1:1 cell:bel pin cardinality, as a next step. Signed-off-by: gatecat <gatecat@ds0.me>
* Use 'T' postfix to disambiguate LHS and RHS of usingD. Shah2021-02-081-21/+21
| | | | | | | Arches might otherwise have range types named ambigiously with the entry in ArchRanges. Signed-off-by: D. Shah <dave@ds0.me>
* Add archArgs and archArgsToId to Arch APID. Shah2021-02-051-2/+3
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* gowin: Switch to BaseArchD. Shah2021-02-051-110/+105
| | | | Signed-off-by: D. Shah <dave@ds0.me>
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