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author | YRabbit <rabbit@yrabbit.cyou> | 2022-05-27 22:44:21 +1000 |
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committer | YRabbit <rabbit@yrabbit.cyou> | 2022-05-27 22:44:21 +1000 |
commit | db696af2fe53ab4dc341a09303bb6cd371d76519 (patch) | |
tree | 04c7ffcc0bdda09aec357f7d739e598b07252ad6 /gowin/arch.h | |
parent | 4ecbf6c6e941699413e0d0bba660fc9dc18efcfe (diff) | |
download | nextpnr-db696af2fe53ab4dc341a09303bb6cd371d76519.tar.gz nextpnr-db696af2fe53ab4dc341a09303bb6cd371d76519.tar.bz2 nextpnr-db696af2fe53ab4dc341a09303bb6cd371d76519.zip |
gowin: Add support for long wires
Gowin chips have a highly sophisticated system of long wires that are
wired to each cell and allow the clock or logic to spread quickly.
This commit implements some of the capabilities of the long wire system
for quadrants, leaving out the fine-tuning of them for each column.
To make use of the long wire system, the specified wire is cut at the
driver and a special cell is placed between the driver and the rest of
the wire.
* VCC and GND can not use long wires because they are in every cell and
there is no point in using a net
* Long wire numbers can be specified manually or assigned automatically.
* The route from the driver to the port of the new cell can be quite
long, this will have to be solved somehow.
* It might make sense to add a mechanism for automatically finding
candidates for long wires.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Diffstat (limited to 'gowin/arch.h')
-rw-r--r-- | gowin/arch.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/gowin/arch.h b/gowin/arch.h index 14181d79..8bbbd514 100644 --- a/gowin/arch.h +++ b/gowin/arch.h @@ -459,6 +459,9 @@ struct Arch : BaseArch<ArchRanges> void assignArchInfo() override; bool cellsCompatible(const CellInfo **cells, int count) const; bool haveBelType(int x, int y, IdString bel_type); + bool allocate_longwire(NetInfo *ni, int lw_idx = -1); + void fix_longwire_bels(); + // chip db version unsigned int const chipdb_version = 1; @@ -475,6 +478,9 @@ struct Arch : BaseArch<ArchRanges> // XXX GW1NR-9 iobuf quirk bool gw1n9_quirk = false; + // 8 Long wires + uint8_t avail_longwires = 0xff; + // Permissible combinations of modes in a single slice std::map<const IdString, IdString> dff_comp_mode; }; @@ -487,7 +493,9 @@ enum iologic_0_z = 20, // start Z for the IOLOGIC bels vcc_0_z = 277, // virtual VCC bel Z gnd_0_z = 278, // virtual VSS bel Z - osc_z = 280 // Z for the oscillator bels + osc_z = 280, // Z for the oscillator bels + bufs_0_z = 281, // Z for long wire buffer bel + free_z = 289 // Must be the last, one can use z starting from this value, adjust accordingly. }; } |