aboutsummaryrefslogtreecommitdiffstats
path: root/fpga_interchange/dedicated_interconnect.cc
Commit message (Collapse)AuthorAgeFilesLines
* interchange: Fix compile warningsgatecat2021-09-281-1/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Skip IO ports in dedicated routing checkgatecat2021-07-121-0/+8
| | | | | | These have already been dealt with in arch_pack_io Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Debug IO port validity check failuresgatecat2021-07-121-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: reduce run-time to check dedicated interconnectAlessandro Comodi2021-07-081-1/+61
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: fix dedicated interconnect explorationAlessandro Comodi2021-06-301-8/+14
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: Fix dedicated interconnect check when site is the samegatecat2021-06-301-1/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Handle disconnected bel pins in dedicated interconnectgatecat2021-06-281-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Cope with undriven nets in more placesgatecat2021-06-141-4/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Using hashlib in archesgatecat2021-06-021-3/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fix bug where DedicateInterconnect incorrectly allows some placement.Keith Rothman2021-03-301-9/+22
| | | | | | | This occurs when the driver pin and sink pin are part of the same site, but not reachable with site routing only. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Implement debugging tools for site router.Keith Rothman2021-03-251-0/+29
| | | | | | | | - Finishes implementation of SiteArch::nameOfPip and SiteArch::nameOfWire - Adds "explain_bel_status", which should be an exhaustive diagnostic of the status of a BEL placement. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix compiler warnings introduced by -Wextragatecat2021-02-251-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fix assorted bugs in FPGA interchange.Keith Rothman2021-02-231-264/+260
| | | | | | | | | | Fixes: - Only use map constant pins during routing, and not during placement. - Unmapped cell ports have no BEL pins. - Fix SiteRouter congestion not taking into account initial expansion. - Fix psuedo-site pip output. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Finish dedicated interconnect implementation.Keith Rothman2021-02-231-128/+566
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial logic for handling dedicated interconnect situations.Keith Rothman2021-02-231-0/+351
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-20 14:46:23 +0000