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author | gatecat <gatecat@ds0.me> | 2021-06-02 10:01:36 +0100 |
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committer | gatecat <gatecat@ds0.me> | 2021-06-02 15:05:19 +0100 |
commit | ecc19c2c083f7e3ed7da95557731ded803d2cb1d (patch) | |
tree | 864780d38cb9a49b6846a0045ac93e1b4dfcc88d /fpga_interchange/dedicated_interconnect.cc | |
parent | f4fed62c05a9595e22a8ec54add5531225911741 (diff) | |
download | nextpnr-ecc19c2c083f7e3ed7da95557731ded803d2cb1d.tar.gz nextpnr-ecc19c2c083f7e3ed7da95557731ded803d2cb1d.tar.bz2 nextpnr-ecc19c2c083f7e3ed7da95557731ded803d2cb1d.zip |
Using hashlib in arches
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'fpga_interchange/dedicated_interconnect.cc')
-rw-r--r-- | fpga_interchange/dedicated_interconnect.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/fpga_interchange/dedicated_interconnect.cc b/fpga_interchange/dedicated_interconnect.cc index 9f7e83ab..2f6fbcd3 100644 --- a/fpga_interchange/dedicated_interconnect.cc +++ b/fpga_interchange/dedicated_interconnect.cc @@ -496,7 +496,7 @@ void DedicatedInterconnect::find_dedicated_interconnect() } } - std::unordered_set<TileTypeBelPin> seen_pins; + pool<TileTypeBelPin> seen_pins; for (auto sink_pair : sinks) { for (auto src : sink_pair.second) { seen_pins.emplace(src.type_bel_pin); @@ -558,7 +558,7 @@ void DedicatedInterconnect::expand_sink_bel(BelId sink_bel, IdString sink_pin, W nodes_to_expand.push_back(wire_node); Loc sink_loc = ctx->getBelLocation(sink_bel); - std::unordered_set<DeltaTileTypeBelPin> srcs; + pool<DeltaTileTypeBelPin> srcs; while (!nodes_to_expand.empty()) { WireNode node_to_expand = nodes_to_expand.back(); @@ -701,7 +701,7 @@ void DedicatedInterconnect::expand_source_bel(BelId src_bel, IdString src_pin, W nodes_to_expand.push_back(wire_node); Loc src_loc = ctx->getBelLocation(src_bel); - std::unordered_set<DeltaTileTypeBelPin> dsts; + pool<DeltaTileTypeBelPin> dsts; while (!nodes_to_expand.empty()) { WireNode node_to_expand = nodes_to_expand.back(); |