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path: root/fpga_interchange/arch.h
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* Use NEXTPNR_NAMESPACE macro's now that headers are seperated.Keith Rothman2021-03-151-1/+1
* Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-151-7/+9
* Initial LUT rotation logic.Keith Rothman2021-02-261-1/+34
* Fix assorted bugs in FPGA interchange.Keith Rothman2021-02-231-33/+21
* Working FF example now that constant merging is done.Keith Rothman2021-02-231-1/+3
* Add initial logic for handling dedicated interconnect situations.Keith Rothman2021-02-231-5/+9
* Fix reference copy.Keith Rothman2021-02-231-6/+6
* Run "make clangformat".Keith Rothman2021-02-231-6/+8
* Initial working constant network support!Keith Rothman2021-02-231-4/+32
* Add initial constant network support to FPGA interchange arch.Keith Rothman2021-02-231-6/+46
* Change CellInfo in getBelPinsForCellPin to be const.Keith Rothman2021-02-231-1/+1
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-14/+4
* Fix sign mismatch.Keith Rothman2021-02-181-1/+1
* Add some utility methods for site instance access.Keith Rothman2021-02-181-5/+37
* Refactor "get only from iterator" to a utility.Keith Rothman2021-02-171-1/+5
* Continue fixes.Keith Rothman2021-02-171-10/+3
* Add initial site router.Keith Rothman2021-02-171-4/+58
* Working on standing up initial constraints system.Keith Rothman2021-02-171-14/+177
* Merge pull request #586 from litghost/add_cell_bel_mapping_onlygatecat2021-02-171-6/+105
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| * [FPGA Interchange] Add Cell -> BEL Pin maps.Keith Rothman2021-02-161-6/+105
* | Remove isValidBelForCellgatecat2021-02-161-11/+0
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* Add FPGA interchange frontend and backend.Keith Rothman2021-02-151-0/+10
* Merge pull request #575 from YosysHQ/gatecat/belpin-2gatecat2021-02-151-0/+3
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| * Add getBelPinsForCellPin to Arch APIgatecat2021-02-101-0/+3
* | Add FPGA interchange XDC parser.Keith Rothman2021-02-121-1/+4
* | Add getBelHidden and add some missing "override" statements.Keith Rothman2021-02-111-2/+1
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* interchange: Base on ArchAPID. Shah2021-02-081-103/+134
* Add RelSlice::ssize and use it when comparing with signed ints.Keith Rothman2021-02-051-13/+14
* Move all string data into BBA file.Keith Rothman2021-02-051-6/+7
* Use RelSlice instead of RelPtr in cases where sizes are present.Keith Rothman2021-02-041-80/+50
* Update APIs to conform to style guide.Keith Rothman2021-02-041-52/+55
* Remove unused method getReservedWireNet.Keith Rothman2021-02-041-7/+0
* Update copywrite headers.Keith Rothman2021-02-041-1/+2
* Run "make clangformat".Keith Rothman2021-02-041-104/+73
* Update FPGA interchange to use IdStringList.Keith Rothman2021-02-041-32/+25
* Start adding data for placement constraint solving.Keith Rothman2021-02-041-5/+22
* Debug BEL bucket data.Keith Rothman2021-02-041-11/+14
* Add initial updates to FPGA interchange arch for BEL buckets.Keith Rothman2021-02-041-0/+204
* Address review comments.Keith Rothman2021-02-041-0/+1
* Fix BBA import bugs.Keith Rothman2021-02-041-21/+46
* Assorted fixes to new FPGA interchange based arch.Keith Rothman2021-02-041-1/+1
* Initial compiling version.Keith Rothman2021-02-041-16/+16
* Initial FPGA interchange (which is just a cut-down xilinx arch).Keith Rothman2021-02-041-0/+1096