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* clangformatgatecat2021-04-121-9/+10
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Disambiguate cell and bel pins when creating Vcc tiesgatecat2021-04-091-6/+10
| | | | | | | | | | | | The pins created for tieing to Vcc were being named after the bel pin, relying on the fact that Xilinx names cell and bel pins differently for LUTs. This isn't true for Nexus devices which uses the same names for both, and was causing a failure as a result. This uses a "PHYS_" prefix that's highly unlikely to appear in a cell pin name to disambiguate. Signed-off-by: gatecat <gatecat@ds0.me>
* [interchange] Provide estimateDelay when USE_LOOKAHEAD is not defined.Keith Rothman2021-04-061-1/+16
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Remove requirement to have wire_lut.Keith Rothman2021-04-061-6/+0
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Scale edge cost of pseudo pips.Keith Rothman2021-04-061-0/+11
| | | | | | | Previous pseudo pips were the same cost as regular pips, but this is definitely too fast, and meant that the router was prefering them. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Disallow site edges during general routing.Keith Rothman2021-04-061-5/+22
| | | | | | | This prevents the general router from routing through sites, which is not legal in FPGA interchange. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Add crude pseudo pip model.Keith Rothman2021-04-061-4/+35
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Update to v6 of FPGA interchange chipdb.Keith Rothman2021-04-011-1/+6
| | | | | | | Changes: - Adds LUT output pin to LutBelPOD. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Fix site pip check for drivers.Keith Rothman2021-03-301-7/+22
| | | | | | Previous code allowed router to entire sites with no sinks. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Implement debugging tools for site router.Keith Rothman2021-03-251-0/+30
| | | | | | | | - Finishes implementation of SiteArch::nameOfPip and SiteArch::nameOfWire - Adds "explain_bel_status", which should be an exhaustive diagnostic of the status of a BEL placement. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Re-work LUT mapping logic to only put VCC pins when required.Keith Rothman2021-03-251-98/+35
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fixup some of the re-mapping logic.Keith Rothman2021-03-251-24/+74
| | | | | | | - Add IDEMPOTENT_CHECK define to perform some expected idempotent operations more than once to verify they work as expected. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial handling of local site inverters and constant signals.Keith Rothman2021-03-251-20/+95
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #643 from litghost/id_constantsgatecat2021-03-231-4/+25
|\ | | | | [FPGA interchange] Convert some string constants to IdString.
| * [FPGA interchange] Convert some string constants to IdString.Keith Rothman2021-03-231-4/+25
| | | | | | | | | | | | Also add some optional diagnostic prints for cell -> BEL pin mapping. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Initial version of inverter logic.Keith Rothman2021-03-231-0/+31
| | | | | | | | | | | | | | For now just implements some inspection capabilities, and the site router (for now) avoids inverted paths. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Use new parameter definition data in FPGA interchange processing.Keith Rothman2021-03-231-41/+5
|/ | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial lookahead for FPGA interchange.Keith Rothman2021-03-231-13/+39
| | | | | | | | | Currently the lookahead is disabled by default because of the time to compute and RAM usage. However it does appear to work reasonably well in testing. Further effort is required to lower RAM usage after initial computation, and explore trade-off for cheaper time to compute. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #637 from litghost/refine_site_routergatecat2021-03-221-2/+30
|\ | | | | Refine site router
| * Rework FPGA interchange site router.Keith Rothman2021-03-221-2/+30
| | | | | | | | | | | | | | The new site router should be robust to most situations, and isn't significantly slower with the use of caching. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Add "checkPipAvailForNet" to Arch API.Keith Rothman2021-03-221-2/+2
|/ | | | | | | | This is important for distiguishing valid pseudo pips in the FPGA interchange arch. This also avoids a double or triple lookup of pip->net map. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add pseudo pip data to chipdb (with schema bump).Keith Rothman2021-03-221-5/+127
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Refactor header structures in FPGA interchange Arch.Keith Rothman2021-03-191-9/+285
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Use NEXTPNR_NAMESPACE macro's now that headers are seperated.Keith Rothman2021-03-151-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* clangformatgatecat2021-03-031-1/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Initial LUT rotation logic.Keith Rothman2021-02-261-1/+196
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix assorted bugs in FPGA interchange.Keith Rothman2021-02-231-85/+158
| | | | | | | | | | Fixes: - Only use map constant pins during routing, and not during placement. - Unmapped cell ports have no BEL pins. - Fix SiteRouter congestion not taking into account initial expansion. - Fix psuedo-site pip output. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Finish dedicated interconnect implementation.Keith Rothman2021-02-231-9/+36
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Working FF example now that constant merging is done.Keith Rothman2021-02-231-5/+182
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial logic for handling dedicated interconnect situations.Keith Rothman2021-02-231-0/+5
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Remove some signedness warnings.Keith Rothman2021-02-231-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial constant network support to FPGA interchange arch.Keith Rothman2021-02-231-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-1/+1
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* Add some utility methods for site instance access.Keith Rothman2021-02-181-2/+2
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Refactor "get only from iterator" to a utility.Keith Rothman2021-02-171-5/+2
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Change how package pin IO sites are selected.Keith Rothman2021-02-171-1/+17
| | | | | | | The first site type that matches is now selected, under the premise that the early site types are more general. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Continue fixes.Keith Rothman2021-02-171-0/+12
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial site router.Keith Rothman2021-02-171-1/+1
| | | | | | | | This site router likely cannot handle the full problem space. It may need to be replaced with a more generalize approach as testing continues. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Working on standing up initial constraints system.Keith Rothman2021-02-171-11/+76
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* clangformatgatecat2021-02-171-3/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Require `--package` when arch BBA contains multiple packages.Keith Rothman2021-02-161-3/+11
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [FPGA Interchange] Add Cell -> BEL Pin maps.Keith Rothman2021-02-161-7/+161
| | | | | | | This also expands the FPGA interchange Arch BBA to include placement constraints, but doesn't implement them yet. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add FPGA interchange frontend and backend.Keith Rothman2021-02-151-2/+19
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Run "make clangformat".Keith Rothman2021-02-121-5/+5
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Refactor XDC parser into a little class for testing purposes.Keith Rothman2021-02-121-0/+11
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add FPGA interchange XDC parser.Keith Rothman2021-02-121-0/+7
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* interchange: Base on ArchAPID. Shah2021-02-081-3/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Add RelSlice::ssize and use it when comparing with signed ints.Keith Rothman2021-02-051-14/+14
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Move all string data into BBA file.Keith Rothman2021-02-051-8/+8
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Use RelSlice instead of RelPtr in cases where sizes are present.Keith Rothman2021-02-041-17/+17
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 21:16:14 +0000