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* Improve reporting of unknown cell typesDavid Shah2018-11-291-1/+2
* ecp5: Adding mux support up to LUT6David Shah2018-11-161-1/+2
* ecp5: clangformat timing changesDavid Shah2018-11-161-1/+1
* ecp5: Use speed-grade-specific delay estimateDavid Shah2018-11-161-2/+2
* ecp5: Fix db import, improve timing data debuggingDavid Shah2018-11-161-1/+28
* ecp5: Post-rebase fixDavid Shah2018-11-161-3/+3
* ecp5: Use new timing dataDavid Shah2018-11-161-77/+59
* ecp5: Adding real timing data to databaseDavid Shah2018-11-161-1/+1
* ecp5: Add timing info for SERDESDavid Shah2018-11-151-1/+26
* ecp5: Adding ancillary DCU belsDavid Shah2018-11-151-1/+1
* ecp5: Working on DCUDavid Shah2018-11-151-0/+2
* Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-131-2/+2
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| * Merge pull request #107 from YosysHQ/router_improveEddie Hung2018-11-131-2/+2
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| | * ecp5: Improve delay estimatesDavid Shah2018-11-131-2/+2
* | | ecp5: EBR clocking fixDavid Shah2018-11-121-5/+8
* | | ecp5: Update arch to new timing APIDavid Shah2018-11-121-13/+62
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* / show 4th tresllis_io in tile boundsMiodrag Milanovic2018-11-111-1/+1
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* ecp5: Add PLL supportDavid Shah2018-10-311-0/+2
* ecp5: Adding DSP supportDavid Shah2018-10-211-0/+4
* ecp5: Implement ECP5 equivalent of c9059fcDavid Shah2018-10-211-0/+9
* clangformatDavid Shah2018-10-161-2/+4
* ecp5: Add support for correct tile naming in all variantsDavid Shah2018-10-161-3/+27
* ecp5: Add DP16KD timing analysisDavid Shah2018-10-161-2/+29
* ecp5: Dummy timing entry for BRAMDavid Shah2018-10-051-0/+3
* clangformatDavid Shah2018-10-011-1/+1
* ecp5: Remove broken DRAM timing arcDavid Shah2018-10-011-2/+2
* clangformatDavid Shah2018-09-291-4/+4
* ecp5: Fix global buffer connectivity and timingDavid Shah2018-09-291-0/+12
* ecp5: Global router produces a working bitstreamDavid Shah2018-09-291-0/+2
* ecp5: Integrate global router and debug namingDavid Shah2018-09-291-1/+5
* ecp5: Add DCC Bels, fix global router post-rebaseDavid Shah2018-09-291-0/+1
* ecp5: Helper function and arch tweaks for global routerDavid Shah2018-09-291-0/+6
* ecp5: clangformatDavid Shah2018-08-191-27/+19
* ecp5: Fix delay heuristicDavid Shah2018-08-191-2/+2
* ecp5: Add cell delaysDavid Shah2018-08-191-11/+131
* Merge pull request #54 from daveshah1/ecp5_speedupDavid Shah2018-08-191-1/+3
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| * ecp5: Flatten bel_to_cell for performanceDavid Shah2018-08-181-1/+3
* | Merge pull request #47 from YosysHQ/settings_propagateClifford Wolf2018-08-181-6/+2
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| * Use settings for placer1 and router1Miodrag Milanovic2018-08-091-6/+2
* | ecp5: Speedup router with slightly better estimatesDavid Shah2018-08-181-2/+2
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* Merge branch 'master' of github.com:YosysHQ/nextpnr into constidsClifford Wolf2018-08-081-4/+4
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| * Arch API: Removing Arch::isIOCellDavid Shah2018-08-081-2/+0
| * Arch API: New specification for timing port classesDavid Shah2018-08-081-3/+4
| * clangformatEddie Hung2018-08-061-6/+1
| * Add Arch::isIOCell() to ecp5 and genericEddie Hung2018-08-061-0/+6
| * Modify getBudgetOverride for generic and ecp5 tooEddie Hung2018-08-051-1/+1
* | ecp5: Update to use const IdStrings in place of PortPin/BelTypeDavid Shah2018-08-081-57/+15
* | Modify getBudgetOverride for generic and ecp5 tooEddie Hung2018-08-061-1/+1
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* API change: Use CellInfo* and NetInfo* as cell/net handles (ECP5)David Shah2018-08-051-1/+1
* Add constraint weight as a command line optionDavid Shah2018-08-031-1/+1
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