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* cmake: Make HeAP placer always-enabledgatecat2023-03-171-10/+2
* Add remapping of DSP clk/ce/rst signals in a block.Adam Greig2023-01-041-0/+4
* refactor: ArcBounds -> BoundingBoxgatecat2022-12-071-2/+2
* refactor: Use IdString::in instead of || chainsgatecat2022-08-101-44/+32
* refactor: id(stringf(...)) to new idf(...) helpergatecat2022-08-101-4/+4
* ecp5: Tweak delay predictiongatecat2022-04-201-1/+1
* ecp5: Split the SLICE bel into separate LUT/FF/RAMW belsgatecat2022-04-071-55/+92
* refactor: Use constids instead of id("..")gatecat2022-02-161-19/+18
* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-191-13/+8
* ecp5: LUT permutation supportgatecat2021-12-131-0/+4
* ecp5: Use a vector rather than dictMatt Johnston2021-12-121-0/+21
* ecp5: Add DCSC supportgatecat2021-07-061-0/+12
* Fixing old emails and names in copyrightsgatecat2021-06-121-2/+2
* ecp5: Add missing clock edge assignmentsgatecat2021-06-101-0/+2
* Add relative constraints to position MULT18X18D near connected ALU54B.Adam Greig2021-04-291-0/+5
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-23/+20
* Merge pull request #568 from YosysHQ/dave/arch-overridegatecat2021-02-081-12/+2
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| * Rename ArchBase to BaseArch for consistency with BaseCtxD. Shah2021-02-051-2/+2
| * Add default implementation of bel bucket functionsD. Shah2021-02-051-12/+2
* | Use RelSlice::ssize instead of cast-to-int throughoutD. Shah2021-02-081-6/+6
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* ecp5: Use snake case for arch-specific functionsD. Shah2021-02-031-48/+47
* ecp5: Implement IdStringList for all arch object namesD. Shah2021-02-021-58/+46
* ecp5: Proof-of-concept using IdStringList for bel namesD. Shah2021-02-021-3/+12
* Run "make clangformat".Keith Rothman2021-02-021-2/+2
* Rename Partition -> BelBucket.Keith Rothman2021-02-021-3/+3
* Working compile of ECP5.Keith Rothman2021-02-021-1/+1
* Refactor ECP5 to new Partition API.Keith Rothman2021-02-021-0/+13
* cleanup: Remove dead/unused codeD. Shah2021-01-281-25/+0
* ecp5: Switch from RelPtr to RelSliceD. Shah2021-01-271-67/+53
* ecp5: Fix FF timing dataDavid Shah2020-12-171-4/+4
* Fix clangformat and execute itMiodrag Milanovic2020-06-271-12/+8
* Simplify and improve chipdb embedding/loading.whitequark2020-06-261-49/+33
* CMake: rewrite chipdb handling from ground up.whitequark2020-06-251-2/+2
* Port nextpnr-{ice40,ecp5} to WASI.whitequark2020-05-231-2/+3
* ecp5: MULT18X18D timing fixesDavid Shah2020-05-011-10/+26
* No cell delay for clocked MULT18X18DRoss Schlaikjer2020-04-301-0/+2
* Issue warning for mixed-mode inputsRoss Schlaikjer2020-04-291-24/+11
* Handle register timing caseRoss Schlaikjer2020-04-291-6/+58
* Use registered port class on mult18x18Ross Schlaikjer2020-04-291-3/+5
* Alter MULT18X18D timing db based on register configRoss Schlaikjer2020-04-281-1/+1
* Merge pull request #423 from rschlaikjer/rschlaikjer-regmode-timing-databaseDavid Shah2020-04-071-4/+2
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| * Actually just move all the logic to ArchInfoRoss Schlaikjer2020-04-071-15/+2
| * Extract regmode configuration to ArchInfoRoss Schlaikjer2020-04-071-8/+4
| * Change timing database lookup based on REGMODE valueRoss Schlaikjer2020-04-071-4/+19
* | ecp5: Proper support for '12k' deviceDavid Shah2020-03-131-2/+7
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* router2: Improve flow and log outputDavid Shah2020-02-031-1/+1
* Allow selection of router algorithmDavid Shah2020-02-031-2/+16
* router2: Make magic numbers configurableDavid Shah2020-02-031-1/+1
* ecp5: Improve bounding box accuracyDavid Shah2020-02-031-4/+19
* ecp5: router2 main renameDavid Shah2020-02-031-1/+1
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