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authorDavid Shah <dave@ds0.me>2018-10-16 13:30:23 +0100
committerDavid Shah <dave@ds0.me>2018-10-16 13:30:23 +0100
commit3aa3f5d796c8ac191ca95181da4c2476bd7d1660 (patch)
tree1c8221c7c5410811faa1fca0f32d09d99b32e2cb /ecp5/arch.cc
parent1fc2318c530f85e6c3fe93d7459646b4cfdff68f (diff)
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ecp5: Add DP16KD timing analysis
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'ecp5/arch.cc')
-rw-r--r--ecp5/arch.cc31
1 files changed, 29 insertions, 2 deletions
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index b3a40a03..ba7a9e0b 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -19,6 +19,7 @@
*/
#include <algorithm>
+#include <boost/range/adaptor/reversed.hpp>
#include <cmath>
#include <cstring>
#include "gfx.h"
@@ -531,6 +532,19 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
return true;
}
return false;
+ } else if (cell->type == id_DP16KD) {
+ if (fromPort == id_CLKA) {
+ if (toPort.str(this).substr(0, 3) == "DOA") {
+ delay.delay = 4260;
+ return true;
+ }
+ } else if (fromPort == id_CLKB) {
+ if (toPort.str(this).substr(0, 3) == "DOB") {
+ delay.delay = 4280;
+ return true;
+ }
+ }
+ return false;
} else {
return false;
}
@@ -583,8 +597,21 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id
return TMG_COMB_OUTPUT;
return TMG_IGNORE;
} else if (cell->type == id_DP16KD) {
- // FIXME
- return TMG_IGNORE;
+ if (port == id_CLKA || port == id_CLKB)
+ return TMG_CLOCK_INPUT;
+ std::string port_name = port.str(this);
+ for (auto c : boost::adaptors::reverse(port_name)) {
+ if (std::isdigit(c))
+ continue;
+ if (c == 'A')
+ clockPort = id_CLKA;
+ else if (c == 'B')
+ clockPort = id_CLKB;
+ else
+ NPNR_ASSERT_FALSE_STR("bad ram port");
+ return (cell->ports.at(port).type == PORT_OUT) ? TMG_REGISTER_OUTPUT : TMG_REGISTER_INPUT;
+ }
+ NPNR_ASSERT_FALSE_STR("no timing type for RAM port '" + port.str(this) + "'");
} else {
NPNR_ASSERT_FALSE_STR("no timing data for cell type '" + cell->type.str(this) + "'");
}