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| * Correct Not Equal operator implementation in ice40Tyler2022-10-171-1/+1
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* Merge pull request #1032 from davidlattimore/registered-output-xformmyrtle2022-10-052-0/+9
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| * nexus: Transform registered output parametersDavid Lattimore2022-10-052-0/+9
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* Merge pull request #1031 from YosysHQ/gatecat/fab-nextmyrtle2022-09-305-2/+130
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| * fabulous: Pack, validity check and FASM support for muxesgatecat2022-09-304-5/+84
| * fabulous: Add split MUX belsgatecat2022-09-302-1/+50
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* Merge pull request #1030 from YosysHQ/gatecat/ice40-dsp25_10-fixmyrtle2022-09-261-15/+21
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| * ice40: Fix handling of carry out route-thru via 25,14gatecat2022-09-261-15/+21
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* Merge pull request #1029 from airskywater/airskywater-patch-1myrtle2022-09-241-0/+6
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| * Modify code to meet the code style preferencesairskywater2022-09-241-4/+4
| * Add more sanity check for pointersairskywater2022-09-241-0/+1
| * fix runtime segmentation faultairskywater2022-09-241-0/+5
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* Merge pull request #1019 from antmicro/support-clock-relationsmyrtle2022-09-204-11/+300
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| * Added the --ignore-rel-clk option to control timing checks for cross-domain p...Maciej Kurc2022-09-203-115/+108
| * Code cleanupMaciej Kurc2022-08-312-68/+39
| * Added timing check for cross-domain paths for related clocksMaciej Kurc2022-08-311-4/+104
| * Augmented TimingAnalyser class with detection of clock to clock relationsMaciej Kurc2022-08-302-7/+225
| * Fixed port timing classes of DCC ports in the Nexus architectureMaciej Kurc2022-08-301-4/+11
* | Merge pull request #1028 from YosysHQ/gatecat/router2-reserve-srcmyrtle2022-09-202-0/+17
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| * | ice40: implement checkPipAvailForNetgatecat2022-09-201-0/+10
| * | router2: Reserve source wire, toogatecat2022-09-201-0/+7
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* | fabulous: fix, but disable, IO configurationgatecat2022-09-161-0/+3
* | Merge pull request #1026 from YosysHQ/gatecat/ecp5-bitstream-refactormyrtle2022-09-161-1347/+1402
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| * | ecp5: Split bitstream generation into more functionsgatecat2022-09-151-1347/+1402
* | | Merge pull request #1023 from YosysHQ/gatecat/ice40up-bram-polmyrtle2022-09-161-3/+7
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| * | | ice40: Fix UltraPlus BRAM clock polaritygatecat2022-09-141-3/+7
* | | | Merge pull request #1025 from YosysHQ/gatecat/nexus-dev-fixesmyrtle2022-09-153-1/+42
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| * | | nexus: Add ES2 device names and --list-devicesgatecat2022-09-153-1/+42
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* | | Merge pull request #1015 from YosysHQ/gatecat/fabulous-viaductmyrtle2022-09-1512-1/+1637
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| * | | fabulous: Add a viaduct uarchgatecat2022-09-0912-1/+1637
* | | | Merge pull request #1024 from YosysHQ/gatecat/pybind11-bumpmyrtle2022-09-15214-10025/+21644
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| * | | 3rdparty: Bump vendored pybind11 version for py3.11 supportgatecat2022-09-14214-10025/+21644
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* | | Merge pull request #1018 from yrabbit/bf-0myrtle2022-08-251-0/+2
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| * | gowin: BUGFIX. Really memorize the chipYRabbit2022-08-251-0/+2
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* | Merge pull request #1017 from YosysHQ/routerfixmyrtle2022-08-222-5/+4
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| * | add missing overridesMiodrag Milanovic2022-08-221-3/+3
| * | Fix parameter orderMiodrag Milanovic2022-08-221-2/+1
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* | Merge pull request #1016 from atsampson/python3myrtle2022-08-217-16/+16
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| * | Use CMake's Python3 rather than PythonInterp in subdirsAdam Sampson2022-08-217-16/+16
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* | pybindings: Mark CellInfo::bel as readonlygatecat2022-08-181-2/+1
* | Merge pull request #1014 from LAK132/mastermyrtle2022-08-181-4/+4
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| * Replace deprecated method of finding Python 3LAK1322022-08-171-4/+4
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* Merge pull request #1013 from YosysHQ/gatecat/viaduct-argsmyrtle2022-08-151-0/+14
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| * viaduct: Allow passing command line options to uarch with -ogatecat2022-08-151-0/+14
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* Merge pull request #1012 from YosysHQ/gatecat/refactor-id-inmyrtle2022-08-1124-203/+153
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| * refactor: Use IdString::in instead of || chainsgatecat2022-08-1024-203/+153
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* Merge pull request #1011 from YosysHQ/gatecat/nexus-lram-tmgmyrtle2022-08-103-0/+30
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| * nexus: Add timing data for LRAMgatecat2022-08-103-0/+30
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* Merge pull request #1010 from YosysHQ/gatecat/idfmyrtle2022-08-1022-153/+152
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| * refactor: id(stringf(...)) to new idf(...) helpergatecat2022-08-1022-153/+152
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