aboutsummaryrefslogtreecommitdiffstats
path: root/ice40
diff options
context:
space:
mode:
authormyrtle <gatecat@ds0.me>2022-09-20 14:37:55 +0200
committerGitHub <noreply@github.com>2022-09-20 14:37:55 +0200
commit136ab81cbd9cac143987d3d8d1603f13a8353abc (patch)
tree84cbc0a284520cf809ff3e6d3c27194db9e01afa /ice40
parent376cedd558f6aaf7fa460c4560cb5e45d41f0a62 (diff)
parenta920ffcf70dad54596c84079c30a66542022ccda (diff)
downloadnextpnr-136ab81cbd9cac143987d3d8d1603f13a8353abc.tar.gz
nextpnr-136ab81cbd9cac143987d3d8d1603f13a8353abc.tar.bz2
nextpnr-136ab81cbd9cac143987d3d8d1603f13a8353abc.zip
Merge pull request #1028 from YosysHQ/gatecat/router2-reserve-src
router2: Reserve source wire, too; ice40 fixes
Diffstat (limited to 'ice40')
-rw-r--r--ice40/arch.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/ice40/arch.h b/ice40/arch.h
index 3563baad..5ed2347d 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -680,6 +680,16 @@ struct Arch : BaseArch<ArchRanges>
return switches_locked[pi.switch_index] == WireId();
}
+ bool checkPipAvailForNet(PipId pip, NetInfo *net) const override
+ {
+ if (ice40_pip_hard_unavail(pip))
+ return false;
+
+ auto &pi = chip_info->pip_data[pip.index];
+ auto swl = switches_locked[pi.switch_index];
+ return swl == WireId() || (swl == getPipDstWire(pip) && wire_to_net[swl.index] == net);
+ }
+
NetInfo *getBoundPipNet(PipId pip) const override
{
NPNR_ASSERT(pip != PipId());