From 32f2ec86c4b83d1e0f3c0982566ff4de30edebb3 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Fri, 19 Mar 2021 18:26:00 -0700 Subject: Rework FPGA interchange site router. The new site router should be robust to most situations, and isn't significantly slower with the use of caching. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- fpga_interchange/arch.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'fpga_interchange/arch.h') diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h index 6a3d7ad1..005bbb41 100644 --- a/fpga_interchange/arch.h +++ b/fpga_interchange/arch.h @@ -37,6 +37,7 @@ #include "chipdb.h" #include "dedicated_interconnect.h" #include "site_router.h" +#include "site_routing_cache.h" NEXTPNR_NAMESPACE_BEGIN @@ -1037,6 +1038,8 @@ struct Arch : ArchAPI std::regex verilog_hex_constant; void read_lut_equation(DynamicBitarray<> *equation, const Property &equation_parameter) const; bool route_vcc_to_unused_lut_pins(); + mutable RouteNodeStorage node_storage; + mutable SiteRoutingCache site_routing_cache; }; NEXTPNR_NAMESPACE_END -- cgit v1.2.3