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Author
Age
Files
Lines
*
synth: report values in bound errors
Tristan Gingold
2023-01-12
2
-9
/
+40
*
synth: use same wording for direction mismatch as simulation
Tristan Gingold
2023-01-12
1
-1
/
+2
*
synth-vhdl_eval: handle to_X01 for bit to std_ulogic.
Tristan Gingold
2023-01-11
3
-0
/
+39
*
synth: handle entity attributes
Tristan Gingold
2023-01-11
1
-2
/
+18
*
synth: handle universal r*i and i*r mul, physical mod.
Tristan Gingold
2023-01-11
1
-1
/
+9
*
synth: handle element attribute
Tristan Gingold
2023-01-11
4
-9
/
+39
*
synth: fix matching comparaison tables
Tristan Gingold
2023-01-11
1
-27
/
+27
*
synth: rework error handling in file operations
Tristan Gingold
2023-01-11
3
-43
/
+63
*
simul: avoid a crash after an error in a condition
Tristan Gingold
2023-01-11
1
-1
/
+6
*
synth: improve support of PSL endpoints
Tristan Gingold
2023-01-11
4
-4
/
+8
*
synth: avoid a crash on very large object types
Tristan Gingold
2023-01-11
1
-0
/
+3
*
synth: check float ranges in subtype conversion
Tristan Gingold
2023-01-11
3
-2
/
+25
*
simul: allow function calls in signal association by value
Tristan Gingold
2023-01-11
1
-0
/
+2
*
synth: add a check for v87 concatenations
Tristan Gingold
2023-01-11
1
-1
/
+6
*
synth: support constant declarations in protected types
Tristan Gingold
2023-01-11
1
-0
/
+1
*
vhdl-configuration: relax top-level unit restrictions
Tristan Gingold
2023-01-11
1
-4
/
+5
*
synth: handle file subtype
Tristan Gingold
2023-01-11
2
-1
/
+9
*
simul: improve support of psl in debugger
Tristan Gingold
2023-01-11
2
-4
/
+13
*
simul: handle psl assume directives
Tristan Gingold
2023-01-11
1
-0
/
+2
*
simul: add sensitivity for psl processes
Tristan Gingold
2023-01-11
1
-4
/
+7
*
synth: allow file declaration in protected objects
Tristan Gingold
2023-01-11
1
-1
/
+2
*
elab-vhdl_files: remove incorrect assertion
Tristan Gingold
2023-01-11
1
-1
/
+0
*
simul: improve assertion messages for psl
Tristan Gingold
2023-01-11
2
-28
/
+45
*
synth: avoid a crash after error on signal association
Tristan Gingold
2023-01-11
1
-2
/
+6
*
simul: add debug command 'run -s'
Tristan Gingold
2023-01-11
3
-8
/
+18
*
simul: handle array element resolution
Tristan Gingold
2023-01-11
1
-1
/
+6
*
synth: also elaborate dependencies of configurations
Tristan Gingold
2023-01-11
1
-0
/
+4
*
simul: improve debugger output
Tristan Gingold
2023-01-11
1
-5
/
+5
*
simul: handle -gGEN=VAL options after the unit
Tristan Gingold
2023-01-11
1
-7
/
+41
*
synth: fix memory allocation in predefined function calls
Tristan Gingold
2023-01-10
3
-1
/
+8
*
synth: adjust unshare_type for unbounded composite types
Tristan Gingold
2023-01-10
1
-4
/
+14
*
synth: check rem/mod by 0
Tristan Gingold
2023-01-10
1
-2
/
+14
*
simul: enable all debug features during elaboration
Tristan Gingold
2023-01-10
2
-5
/
+3
*
synth: handle indexes in arrays conversion
Tristan Gingold
2023-01-10
5
-17
/
+85
*
vhdl-sem_inst: adjust instantiation of interface type
Tristan Gingold
2023-01-10
1
-0
/
+3
*
synth: add comments, minor rewrite
Tristan Gingold
2023-01-10
3
-6
/
+10
*
vhdl-sem_inst: fix build of suspend state chain
Tristan Gingold
2023-01-10
1
-1
/
+1
*
vhdl-prints: handle suspend state declarations and statements
Tristan Gingold
2023-01-10
1
-2
/
+22
*
synth: also fix #2299
Tristan Gingold
2023-01-10
1
-3
/
+6
*
simul: handle inertial assignments
Tristan Gingold
2023-01-10
1
-2
/
+14
*
synth-vhdl_aggr: optimize common aggregate
Tristan Gingold
2023-01-10
2
-17
/
+38
*
Dot output ports (#2305)
cderrien
2023-01-10
1
-53
/
+127
*
synth: always create shared variables
Tristan Gingold
2023-01-09
3
-34
/
+22
*
synth: improve support of individual association for subprograms
Tristan Gingold
2023-01-09
1
-1
/
+2
*
synth-vhdl_aggr: improve support of very large aggregates
Tristan Gingold
2023-01-09
1
-1
/
+2
*
synth: improve support of subtype attribute
Tristan Gingold
2023-01-09
1
-4
/
+4
*
simul: set assertion hook before elaboration
Tristan Gingold
2023-01-09
1
-3
/
+3
*
elab-vhdl_expr(exec_name_subtype): handle image attribute
Tristan Gingold
2023-01-09
1
-0
/
+8
*
simul-vhdl_simul: fix effective value writes
Tristan Gingold
2023-01-09
1
-1
/
+20
*
synth: handle stop/finish without status
Tristan Gingold
2023-01-09
1
-1
/
+3
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