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* synth: detect division by 0, handle universal real/integer divisionTristan Gingold2022-10-021-3/+23
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* synth-vhdl_stmts: handle passive process. Fix ghdl/ghdl-yosys-plugin#174Tristan Gingold2022-10-021-18/+204
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* synth: avoid a crash on literal overflowTristan Gingold2022-10-011-1/+10
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* synth: avoid on crash on overflow in rangesTristan Gingold2022-10-011-0/+8
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* synth: improve handling of individual generic associationsTristan Gingold2022-10-011-17/+22
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* simul: finalize empty proceduresTristan Gingold2022-10-011-9/+11
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* simul: minor rewriteTristan Gingold2022-10-011-3/+2
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* simul: finalize declarations of procedure callsTristan Gingold2022-10-012-0/+6
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* synth: handle read for floatsTristan Gingold2022-09-302-8/+24
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* synth: handle float-float conversionsTristan Gingold2022-09-301-3/+14
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* simul: handle stable attributeTristan Gingold2022-09-302-5/+44
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* synth: factorize codeTristan Gingold2022-09-302-8/+9
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* simul: create disconnectionsTristan Gingold2022-09-301-1/+42
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* libraries.adb: do not set location of entity name of architecture.Tristan Gingold2022-09-301-1/+0
| | | | As the location was the one from the library file, which is unloaded.
* ortho/llvm6: handle llvm 15 (opaque pointers)Tristan Gingold2022-09-291-39/+64
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* simul: handle quiet attributeTristan Gingold2022-09-294-12/+88
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* simul: factorize code, add sub_signal_typeTristan Gingold2022-09-294-92/+73
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* vhdl-canon: extract guard for signal assignment sensitivityTristan Gingold2022-09-291-1/+15
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* simul: support guarded signal assignments (WIP)Tristan Gingold2022-09-291-8/+79
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* synth: handle guard signal in debuggerTristan Gingold2022-09-283-57/+78
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* simul: handle last_value attributeTristan Gingold2022-09-283-1/+31
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* synth: handle guard signal in expressionsTristan Gingold2022-09-282-0/+2
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* simul: fix handling of labels in next/exit statementsTristan Gingold2022-09-281-4/+13
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* synth: handle null-range loopsTristan Gingold2022-09-285-21/+40
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* vhdl-sem: avoid a crash after error. Fix #2201Tristan Gingold2022-09-281-0/+1
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* synth: handle names in record aggregate targetsTristan Gingold2022-09-281-0/+12
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* synth: handle array target aggregateTristan Gingold2022-09-271-2/+6
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* synth: handle error on variable default valueTristan Gingold2022-09-271-0/+5
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* simul: handle null signal assignmentsTristan Gingold2022-09-271-12/+36
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* synth-vhdl_eval: handle nor, nandTristan Gingold2022-09-261-0/+21
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* simul-vhdl_elab: avoid a crash for null-range signalsTristan Gingold2022-09-261-10/+14
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* synth: handle attributes in configurationsTristan Gingold2022-09-264-3/+16
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* synth: improve error checks (type conversion, string literals)Tristan Gingold2022-09-253-33/+37
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* synth: rework error procedure, always pass the instanceTristan Gingold2022-09-2517-254/+406
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* synth-vhdl_eval: handle vhdl-87 array array concatenationTristan Gingold2022-09-251-2/+31
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* vhdl-sem_decls: handle protected type subtypesTristan Gingold2022-09-251-1/+4
| | | | Fix #2196
* vhdl-sem_names: handle architecture bodies in sem_denoting_nameTristan Gingold2022-09-251-1/+2
| | | | Fix #2198
* synth-vhdl_stmts: fix missing newline in default assertion messagesTristan Gingold2022-09-251-3/+3
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* synth: handle default expression for IN variables in assocsTristan Gingold2022-09-251-4/+10
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* synth: handle selected names in targetsTristan Gingold2022-09-251-1/+2
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* synth-vhdl_eval: handle null-null in array concatenationsTristan Gingold2022-09-251-0/+6
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* simul: gather disconnection specifications, create guard signalTristan Gingold2022-09-254-36/+194
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* synth: ignore groups and group templatesTristan Gingold2022-09-253-1/+15
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* grt: do not initialial GUARD signals on creation.Tristan Gingold2022-09-251-1/+4
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* synth: handle attribute namesTristan Gingold2022-09-251-13/+16
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* synth: handle individual subprogram associations for expressionsTristan Gingold2022-09-251-55/+61
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* simul: handle empty proceduresTristan Gingold2022-09-251-1/+9
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* synth: rework association conversionsTristan Gingold2022-09-253-62/+75
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* synth-vhdl_stmts: rework for subprogram associations (WIP)Tristan Gingold2022-09-251-57/+36
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* synth-vhdl_stmts: support of individual paramater associations (WIP)Tristan Gingold2022-09-252-106/+238
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