diff options
author | Tristan Gingold <tgingold@free.fr> | 2022-09-30 07:47:02 +0200 |
---|---|---|
committer | Tristan Gingold <tgingold@free.fr> | 2022-09-30 07:47:02 +0200 |
commit | bd3f2d04cf0cb7d43bb7a823fcbdf2f5b7fdebcc (patch) | |
tree | 0b81aa7e57efdc15be4b8e89ac094dceb350a509 /src | |
parent | fe092cdc810cc559ed484f480d2072c43513a04a (diff) | |
download | ghdl-bd3f2d04cf0cb7d43bb7a823fcbdf2f5b7fdebcc.tar.gz ghdl-bd3f2d04cf0cb7d43bb7a823fcbdf2f5b7fdebcc.tar.bz2 ghdl-bd3f2d04cf0cb7d43bb7a823fcbdf2f5b7fdebcc.zip |
simul: handle stable attribute
Diffstat (limited to 'src')
-rw-r--r-- | src/simul/simul-vhdl_elab.adb | 11 | ||||
-rw-r--r-- | src/simul/simul-vhdl_simul.adb | 38 |
2 files changed, 44 insertions, 5 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 734ff2b2e..34522853f 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -348,6 +348,17 @@ package body Simul.Vhdl_Elab is No_Sensitivity_Index, No_Signal_Index, T, Pfx)); end; + when Iir_Kind_Stable_Attribute => + declare + T : Std_Time; + Pfx : Sub_Signal_Type; + begin + T := Compute_Attribute_Time (Inst, Decl); + Pfx := Compute_Sub_Signal (Inst, Get_Prefix (Decl)); + Gather_Signal ((Mode_Stable, Decl, Inst, null, null, null, + No_Sensitivity_Index, No_Signal_Index, + T, Pfx)); + end; when Iir_Kind_Object_Alias_Declaration => -- In case it aliases a signal. declare diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 0a07fc08b..92fcc920a 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -342,9 +342,7 @@ package body Simul.Vhdl_Simul is return Boolean is begin case Sig.Typ.Kind is - when Type_Logic - | Type_Bit - | Type_Discrete => + when Type_Scalars => declare S : Ghdl_Signal_Ptr; begin @@ -363,9 +361,34 @@ package body Simul.Vhdl_Simul is end if; end case; end; + when Type_Vector + | Type_Array => + declare + Len : constant Uns32 := Sig.Typ.Abound.Len; + Sub : Memory_Ptr; + begin + for I in 1 .. Len loop + Sub := Sig_Index (Sig.Mem, (Len - I) * Sig.Typ.Arr_El.W); + if Read_Signal_Flag ((Sig.Typ.Arr_El, Sub), Kind) then + return True; + end if; + end loop; + return False; + end; + when Type_Record => + declare + Sub : Memory_Ptr; + begin + for I in Sig.Typ.Rec.E'Range loop + Sub := Sig_Index (Sig.Mem, Sig.Typ.Rec.E (I).Offs.Net_Off); + if Read_Signal_Flag ((Sig.Typ.Rec.E (I).Typ, Sub), Kind) then + return True; + end if; + end loop; + return False; + end; when others => raise Internal_Error; - return False; end case; end Read_Signal_Flag; @@ -2505,7 +2528,12 @@ package body Simul.Vhdl_Simul is (To_Ghdl_Value_Ptr (To_Address (E.Val)), E.Time); Write_Sig (E.Sig, S); Register_Prefix (E.Pfx.Typ, To_Memory_Ptr (E.Pfx)); - when Mode_Stable | Mode_Transaction => + when Mode_Stable => + S := Grt.Signals.Ghdl_Create_Stable_Signal + (To_Ghdl_Value_Ptr (To_Address (E.Val)), E.Time); + Write_Sig (E.Sig, S); + Register_Prefix (E.Pfx.Typ, To_Memory_Ptr (E.Pfx)); + when Mode_Transaction => -- Create_Implicit_Signal -- (E.Sig, E.Val, E.Time, E.Prefix, E.Kind); raise Internal_Error; |