simul: factorize code, add sub_signal_type

4 files changed, 73 insertions, 92 deletions

diff --git a/src/simul/simul-vhdl_debug.adb b/src/simul/simul-vhdl_debug.adb
index 5ba294dd3..c54bea94f 100644
--- a/src/simul/simul-vhdl_debug.adb
+++ b/src/simul/simul-vhdl_debug.adb
@@ -91,17 +91,17 @@ package body Simul.Vhdl_Debug is
       Disp_Instance_Path (Processes_Table.Table (D.Proc).Inst);
       New_Line;
       Put ("    noff: ");
-      Put_Uns32 (D.Off.Net_Off);
+      Put_Uns32 (D.Sig.Offs.Net_Off);
       Put (", moff: ");
-      Put_Uns32 (Uns32 (D.Off.Mem_Off));
+      Put_Uns32 (Uns32 (D.Sig.Offs.Mem_Off));
       Put (", len: ");
-      Put_Uns32 (D.Typ.W);
+      Put_Uns32 (D.Sig.Typ.W);
       Put (", typ: ");
-      Debug_Type_Short (D.Typ);
+      Debug_Type_Short (D.Sig.Typ);
       New_Line;
    end Disp_Driver_Entry;
 
-   procedure Disp_Conn_Endpoint (Ep : Connect_Endpoint) is
+   procedure Disp_Conn_Endpoint (Ep : Sub_Signal_Type) is
    begin
       Put ("sig: ");
       Put_Uns32 (Uns32 (Ep.Base));
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb
index 341e33e26..7e37c28d5 100644
--- a/src/simul/simul-vhdl_elab.adb
+++ b/src/simul/simul-vhdl_elab.adb
@@ -175,15 +175,32 @@ package body Simul.Vhdl_Elab is
       Signals_Table.Table (Val.Val.S) := E;
    end Gather_Signal;
 
+   function Compute_Sub_Signal (Inst : Synth_Instance_Acc; Name : Node)
+                               return Sub_Signal_Type
+   is
+      Marker : Mark_Type;
+      Base : Valtyp;
+      Typ : Type_Acc;
+      Off : Value_Offsets;
+      Res : Sub_Signal_Type;
+   begin
+      Mark_Expr_Pool (Marker);
+
+      Synth.Vhdl_Stmts.Synth_Assignment_Prefix (Inst, Name, Base, Typ, Off);
+      Res := (Base => Base.Val.S,
+              Typ => Unshare (Typ, Global_Pool'Access),
+              Offs => Off);
+
+      Release_Expr_Pool (Marker);
+      return Res;
+   end Compute_Sub_Signal;
+
    procedure Gather_Disconnection (Inst : Synth_Instance_Acc; Decl : Node)
    is
       List : constant Node_Flist := Get_Signal_List (Decl);
       Marker : Mark_Type;
       Name : Node;
-      Base_Vt : Valtyp;
-      Typ : Type_Acc;
-      Off : Value_Offsets;
-      Sig : Signal_Index_Type;
+      Sig : Sub_Signal_Type;
       Tval : Valtyp;
       T : Std_Time;
    begin
@@ -192,22 +209,18 @@ package body Simul.Vhdl_Elab is
       Tval := Synth.Vhdl_Expr.Synth_Expression (Inst, Get_Expression (Decl));
       T := Std_Time (Read_Discrete (Tval));
 
+      Release_Expr_Pool (Marker);
+
       for I in Flist_First .. Flist_Last (List) loop
          Name := Get_Nth_Element (List, I);
-         Synth.Vhdl_Stmts.Synth_Assignment_Prefix
-           (Inst, Name, Base_Vt, Typ, Off);
-         Sig := Base_Vt.Val.S;
-         Typ := Unshare (Typ, Global_Pool'Access);
+         Sig := Compute_Sub_Signal (Inst, Name);
          Disconnect_Table.Append
            ((Sig => Sig,
-             Off => Off,
-             Typ => Typ,
              Val => T,
-             Prev => Signals_Table.Table (Sig).Disconnect));
-         Signals_Table.Table (Sig).Disconnect := Disconnect_Table.Last;
+             Prev => Signals_Table.Table (Sig.Base).Disconnect));
+         Signals_Table.Table (Sig.Base).Disconnect := Disconnect_Table.Last;
       end loop;
 
-      Release_Expr_Pool (Marker);
    end Gather_Disconnection;
 
    procedure Gather_Quantity (Inst : Synth_Instance_Acc; Decl : Node)
@@ -376,24 +389,22 @@ package body Simul.Vhdl_Elab is
 
    --  Add a driver for process PROC_IDX on signal SIG at OFF/TYP.
    procedure Add_Process_Driver (Proc_Idx : Process_Index_Type;
-                                 Sig : Signal_Index_Type;
-                                 Off : Value_Offsets;
-                                 Typ : Type_Acc;
+                                 Sig : Sub_Signal_Type;
                                  Loc : Node)
    is
-      S : Signal_Entry renames Signals_Table.Table (Sig);
+      S : Signal_Entry renames Signals_Table.Table (Sig.Base);
       Need_It : Boolean;
    begin
-      pragma Assert (Typ.Wkind = Wkind_Sim);
+      pragma Assert (Sig.Typ.Wkind = Wkind_Sim);
 
-      if Typ.W = 0 then
+      if Sig.Typ.W = 0 then
          --  Be safe: no signal, then no driver.
          return;
       end if;
 
       --  Increment the number of driver for each scalar element.
       Need_It := False;
-      for I in Off.Net_Off .. Off.Net_Off + Typ.W - 1 loop
+      for I in Sig.Offs.Net_Off .. Sig.Offs.Net_Off + Sig.Typ.W - 1 loop
          declare
             Ns : Nbr_Sources_Type renames S.Nbr_Sources (I);
          begin
@@ -419,8 +430,6 @@ package body Simul.Vhdl_Elab is
 
       Drivers_Table.Append
         ((Sig => Sig,
-          Off => Off,
-          Typ => Typ,
           Prev_Sig => S.Drivers,
 
           Proc => Proc_Idx,
@@ -435,31 +444,21 @@ package body Simul.Vhdl_Elab is
      (Inst : Synth_Instance_Acc; Proc : Node; Proc_Idx : Process_Index_Type)
    is
       use Synth.Vhdl_Stmts;
-      Expr_Marker : Mark_Type;
       Driver_List: Iir_List;
       It : List_Iterator;
-      Sig : Node;
-      Base_Vt : Valtyp;
-      Base : Signal_Index_Type;
-      Typ : Type_Acc;
-      Off : Value_Offsets;
+      El : Node;
+      Sig : Sub_Signal_Type;
    begin
-      Mark_Expr_Pool (Expr_Marker);
       Instance_Pool := Process_Pool'Access;
 
       Driver_List := Trans_Analyzes.Extract_Drivers (Proc);
       It := List_Iterate_Safe (Driver_List);
       while Is_Valid (It) loop
-         Sig := Get_Element (It);
-         exit when Sig = Null_Node;
-         Synth_Assignment_Prefix (Inst, Sig, Base_Vt, Typ, Off);
-         Base := Base_Vt.Val.S;
-         Typ := Unshare (Typ, Global_Pool'Access);
+         El := Get_Element (It);
+         exit when El = Null_Node;
+         Sig := Compute_Sub_Signal (Inst, El);
 
-         Release_Expr_Pool (Expr_Marker);
-         pragma Assert (Areapools.Is_Empty (Instance_Pool.all));
-
-         Add_Process_Driver (Proc_Idx, Base, Off, Typ, Sig);
+         Add_Process_Driver (Proc_Idx, Sig, El);
 
          Next (It);
       end loop;
@@ -472,40 +471,29 @@ package body Simul.Vhdl_Elab is
                                  List : Iir_List)
    is
       use Synth.Vhdl_Stmts;
-      Marker : Mark_Type;
       It : List_Iterator;
-      Sig : Node;
-      Base_Vt : Valtyp;
-      Base : Signal_Index_Type;
-      Typ : Type_Acc;
-      Off : Value_Offsets;
+      El : Node;
+      Sig : Sub_Signal_Type;
    begin
-      Mark_Expr_Pool (Marker);
-
       It := List_Iterate_Safe (List);
       while Is_Valid (It) loop
-         Sig := Get_Element (It);
-         exit when Sig = Null_Node;
-         Synth_Assignment_Prefix (Inst, Sig, Base_Vt, Typ, Off);
-         Base := Base_Vt.Val.S;
-         Typ := Unshare (Typ, Global_Pool'Access);
+         El := Get_Element (It);
+         exit when El = Null_Node;
+         Sig := Compute_Sub_Signal (Inst, El);
 
          Sensitivity_Table.Append
-           ((Sig => Base,
-             Off => Off,
-             Typ => Typ,
-             Prev_Sig => Signals_Table.Table (Base).Sensitivity,
+           ((Sig => Sig,
+             Prev_Sig => Signals_Table.Table (Sig.Base).Sensitivity,
 
              Proc => Proc_Idx,
              Prev_Proc => Processes_Table.Table (Proc_Idx).Sensitivity));
 
-         Signals_Table.Table (Base).Sensitivity := Sensitivity_Table.Last;
+         Signals_Table.Table (Sig.Base).Sensitivity := Sensitivity_Table.Last;
          Processes_Table.Table (Proc_Idx).Sensitivity :=
            Sensitivity_Table.Last;
 
          Next (It);
       end loop;
-      Release_Expr_Pool (Marker);
    end Gather_Sensitivity;
 
    procedure Gather_Process_Sensitivity
@@ -568,7 +556,7 @@ package body Simul.Vhdl_Elab is
    end Gather_Process_Sensitivity;
 
    --  Increment the number of sources for EP.
-   procedure Increment_Nbr_Sources (Ep : Connect_Endpoint) is
+   procedure Increment_Nbr_Sources (Ep : Sub_Signal_Type) is
    begin
       if Ep.Typ.W = 0 then
          return;
@@ -602,7 +590,7 @@ package body Simul.Vhdl_Elab is
       Off : Value_Offsets;
       Conn : Connect_Entry;
       List : Iir_List;
-      Formal_Ep, Actual_Ep : Connect_Endpoint;
+      Formal_Ep, Actual_Ep : Sub_Signal_Type;
    begin
       Mark_Expr_Pool (Marker);
       Assoc := Assocs;
@@ -687,16 +675,13 @@ package body Simul.Vhdl_Elab is
                if Formal = Null_Iir then
                   Formal := Inter;
                end if;
-               Synth_Assignment_Prefix
-                 (Port_Inst, Formal, Formal_Base, Typ, Off);
-               Formal_Sig := Formal_Base.Val.S;
-               Formal_Ep := (Formal_Sig, Off, Typ);
+               Formal_Ep := Compute_Sub_Signal (Port_Inst, Formal);
 
                Actual_Ep := (No_Signal_Index, No_Value_Offsets, null);
 
                Conn :=
                  (Formal => Formal_Ep,
-                  Formal_Link => Signals_Table.Table (Formal_Sig).Connect,
+                  Formal_Link => Signals_Table.Table (Formal_Ep.Base).Connect,
                   Actual => Actual_Ep,
                   Actual_Link => No_Connect_Index,
                   Drive_Formal => True, --  Always an IN interface
@@ -707,7 +692,7 @@ package body Simul.Vhdl_Elab is
 
                Connect_Table.Append (Conn);
 
-               Signals_Table.Table (Formal_Sig).Connect :=
+               Signals_Table.Table (Formal_Ep.Base).Connect :=
                  Connect_Table.Last;
 
                if Get_Expr_Staticness (Get_Actual (Assoc)) < Globally then
@@ -719,7 +704,7 @@ package body Simul.Vhdl_Elab is
                       Sensitivity => No_Sensitivity_Index));
 
                   Add_Process_Driver
-                    (Processes_Table.Last, Formal_Sig, Off, Typ, Assoc);
+                    (Processes_Table.Last, Formal_Ep, Assoc);
 
                   List := Create_Iir_List;
                   Vhdl.Canon.Canon_Extract_Sensitivity_Expression
diff --git a/src/simul/simul-vhdl_elab.ads b/src/simul/simul-vhdl_elab.ads
index 233bad313..aff66472a 100644
--- a/src/simul/simul-vhdl_elab.ads
+++ b/src/simul/simul-vhdl_elab.ads
@@ -89,7 +89,7 @@ package Simul.Vhdl_Elab is
    type Connect_Index_Type is new Nat32;
    No_Connect_Index : constant Connect_Index_Type := 0;
 
-   type Connect_Endpoint is record
+   type Sub_Signal_Type is record
       Base : Signal_Index_Type;
       Offs : Value_Offsets;
       Typ : Type_Acc;
@@ -98,11 +98,11 @@ package Simul.Vhdl_Elab is
    --  Connections.  For each associations (block/component/entry), the
    --  elaborator adds an entry in that table.
    type Connect_Entry is record
-      Formal : Connect_Endpoint;
+      Formal : Sub_Signal_Type;
       --  Next connection for the formal.
       Formal_Link : Connect_Index_Type;
 
-      Actual : Connect_Endpoint;
+      Actual : Sub_Signal_Type;
       --  Next connection for the actual.
       Actual_Link : Connect_Index_Type;
 
@@ -168,7 +168,7 @@ package Simul.Vhdl_Elab is
          when Mode_Quiet | Mode_Stable | Mode_Delayed
            | Mode_Transaction =>
             Time : Std_Time;
-            Prefix : Memory_Ptr;
+            Pfx : Sub_Signal_Type;
          when Mode_Above =>
             null;
          when Mode_Guard =>
@@ -187,9 +187,7 @@ package Simul.Vhdl_Elab is
 
    type Driver_Entry is record
       --  The signal having a driver.
-      Sig : Signal_Index_Type;
-      Off : Value_Offsets;
-      Typ : Type_Acc;
+      Sig : Sub_Signal_Type;
       --  Previous driver for the same signal.
       Prev_Sig : Driver_Index_Type;
 
@@ -214,9 +212,7 @@ package Simul.Vhdl_Elab is
       Table_Initial => 128);
 
    type Disconnect_Entry is record
-      Sig : Signal_Index_Type;
-      Off : Value_Offsets;
-      Typ : Type_Acc;
+      Sig : Sub_Signal_Type;
       Prev : Disconnect_Index_Type;
       Val : Std_Time;
    end record;
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb
index ba198c676..b86a4a7d5 100644
--- a/src/simul/simul-vhdl_simul.adb
+++ b/src/simul/simul-vhdl_simul.adb
@@ -321,10 +321,10 @@ package body Simul.Vhdl_Simul is
       while Drv /= No_Driver_Index loop
          declare
             D : Driver_Entry renames Drivers_Table.Table (Drv);
-            S : Signal_Entry renames Signals_Table.Table (D.Sig);
+            S : Signal_Entry renames Signals_Table.Table (D.Sig.Base);
          begin
-            Add_Source
-              (D.Typ, Sig_Index (S.Sig, D.Off.Net_Off), S.Val + D.Off.Mem_Off);
+            Add_Source (D.Sig.Typ, Sig_Index (S.Sig, D.Sig.Offs.Net_Off),
+                        S.Val + D.Sig.Offs.Mem_Off);
 
             Drv := D.Prev_Proc;
          end;
@@ -1433,10 +1433,10 @@ package body Simul.Vhdl_Simul is
                      S : Sensitivity_Entry renames
                        Sensitivity_Table.Table (Sens);
                      Base : constant Memory_Ptr :=
-                       Signals_Table.Table (S.Sig).Sig;
+                       Signals_Table.Table (S.Sig.Base).Sig;
                   begin
                      Add_Wait_Sensitivity
-                       (S.Typ, Sig_Index (Base, S.Off.Net_Off));
+                       (S.Sig.Typ, Sig_Index (Base, S.Sig.Offs.Net_Off));
                      Sens := S.Prev_Proc;
                   end;
                end loop;
@@ -1468,14 +1468,14 @@ package body Simul.Vhdl_Simul is
       Mark : Mark_Type;
       Proc : Proc_Record_Type renames Processes_Table.Table (Proc_Idx);
       Drv : Driver_Entry renames Drivers_Table.Table (Proc.Drivers);
-      Sig : Signal_Entry renames Signals_Table.Table (Drv.Sig);
+      Sig : Signal_Entry renames Signals_Table.Table (Drv.Sig.Base);
       Val : Valtyp;
    begin
       Mark_Expr_Pool (Mark);
       Val := Synth_Expression_With_Type
-        (Proc.Inst, Get_Actual (Proc.Proc), Drv.Typ);
+        (Proc.Inst, Get_Actual (Proc.Proc), Drv.Sig.Typ);
       Assign_Value_To_Signal
-        ((Drv.Typ, Sig.Sig), True, 0, 0, Get_Value_Memtyp (Val));
+        ((Drv.Sig.Typ, Sig.Sig), True, 0, 0, Get_Value_Memtyp (Val));
       Release_Expr_Pool (Mark);
    end Execute_Expression_Association;
 
@@ -1594,9 +1594,9 @@ package body Simul.Vhdl_Simul is
       while Sens /= No_Sensitivity_Index loop
          declare
             S : Sensitivity_Entry renames Sensitivity_Table.Table (Sens);
-            Base : constant Memory_Ptr := Signals_Table.Table (S.Sig).Sig;
+            Base : constant Memory_Ptr := Signals_Table.Table (S.Sig.Base).Sig;
          begin
-            Add_Sensitivity (S.Typ, Sig_Index (Base, S.Off.Net_Off));
+            Add_Sensitivity (S.Sig.Typ, Sig_Index (Base, S.Sig.Offs.Net_Off));
             Sens := S.Prev_Proc;
          end;
       end loop;
@@ -2553,7 +2553,7 @@ package body Simul.Vhdl_Simul is
 
    type Connect_Mode is (Connect_Source, Connect_Effective);
 
-   function To_Memtyp (Ep : Connect_Endpoint) return Memtyp is
+   function To_Memtyp (Ep : Sub_Signal_Type) return Memtyp is
    begin
       return (Ep.Typ,
               Sig_Index (Signals_Table.Table (Ep.Base).Sig, Ep.Offs.Net_Off));