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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-28 06:50:57 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-28 06:52:38 +0200 |
| commit | 2efee206687fae7c8812cf7e094808a6cd733d5b (patch) | |
| tree | 2bfe95f8ca5f607cdb28ad680d9a2a30aa806968 /src | |
| parent | 5993986a91f3f41813b890e6b9d10cc5a3beea17 (diff) | |
| download | ghdl-2efee206687fae7c8812cf7e094808a6cd733d5b.tar.gz ghdl-2efee206687fae7c8812cf7e094808a6cd733d5b.tar.bz2 ghdl-2efee206687fae7c8812cf7e094808a6cd733d5b.zip | |
simul: fix handling of labels in next/exit statements
Diffstat (limited to 'src')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 95048757b..cba9520c4 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -24,7 +24,7 @@ with Utils_IO; with Vhdl.Types; with Vhdl.Errors; -with Vhdl.Utils; +with Vhdl.Utils; use Vhdl.Utils; with Vhdl.Std_Package; with Vhdl.Ieee.Std_Logic_1164; with Vhdl.Sem_Inst; @@ -1092,8 +1092,13 @@ package body Simul.Vhdl_Simul is when Iir_Kind_Exit_Statement => if Execute_Condition (Inst, Get_Condition (Stmt)) then declare - Label : constant Node := Get_Loop_Label (Stmt); + Label : Node; begin + Label := Get_Loop_Label (Stmt); + if Label /= Null_Node then + Label := Get_Named_Entity (Label); + end if; + loop Stmt := Get_Parent (Stmt); case Get_Kind (Stmt) is @@ -1116,8 +1121,13 @@ package body Simul.Vhdl_Simul is when Iir_Kind_Next_Statement => if Execute_Condition (Inst, Get_Condition (Stmt)) then declare - Label : constant Node := Get_Loop_Label (Stmt); + Label : Node; begin + Label := Get_Loop_Label (Stmt); + if Label /= Null_Node then + Label := Get_Named_Entity (Label); + end if; + loop Stmt := Get_Parent (Stmt); case Get_Kind (Stmt) is @@ -1557,7 +1567,6 @@ package body Simul.Vhdl_Simul is return Boolean is use Vhdl.Types; - use Vhdl.Utils; use PSL.Nodes; begin case Get_Kind (Expr) is |