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* synth: handle short-circuit and. Fix #1005Tristan Gingold2019-11-061-9/+38
* files_map-editor: add Copy_Source_File.Tristan Gingold2019-11-062-0/+44
* files_map: add Discard_Source_File, Free_Source_File,Tristan Gingold2019-11-062-5/+44
* files_map-editor: turn Replace_Text to a function.Tristan Gingold2019-11-062-30/+35
* vhdl-ieee-std_logic_1164: minor simplification.Tristan Gingold2019-11-061-21/+8
* synth: handle edge operators in synth_predefined_function_call.Tristan Gingold2019-11-064-31/+24
* vhdl: recognize rising_edge/falling_edge.Tristan Gingold2019-11-062-6/+15
* netlists-dump: avoid a crash on unconnected driver.Tristan Gingold2019-11-061-3/+6
* synth: do not create a value_const of a value_const.Tristan Gingold2019-11-062-1/+6
* synth-expr: do subtype conversion in fill_record_aggregate. Fix #1009Tristan Gingold2019-11-061-1/+2
* synth: unshare default value of variables. Fix #1006Tristan Gingold2019-11-062-4/+42
* netlists-cleanup: do not remove the self-instance.Tristan Gingold2019-11-061-0/+2
* synth-stmts: rewrite target_info to clarify memoryTristan Gingold2019-11-051-18/+56
* synth: do more constant propagation (on build2Tristan Gingold2019-11-054-50/+82
* netlists-disp_vhdl: handle truncate to width 1.Tristan Gingold2019-11-051-2/+7
* netlists-memories: truncate wide addresses.Tristan Gingold2019-11-051-11/+9
* synth-oper: simplify code.Tristan Gingold2019-11-051-7/+4
* netlists: add build2_sresize, simplify code.Tristan Gingold2019-11-053-48/+53
* synth: extract netlists-folds from netlists-builders.Tristan Gingold2019-11-0511-160/+216
* netlists-dump: indent output.Tristan Gingold2019-11-053-13/+17
* netlists-memories: adjust message.Tristan Gingold2019-11-051-1/+1
* netlists: enable expansion.Tristan Gingold2019-11-041-1/+1
* synth-oper: handle constant not.Tristan Gingold2019-11-041-3/+8
* synth-expr: allow constants in discrete rangeTristan Gingold2019-11-041-0/+2
* synth-expr: handle vhdl 2008 aggregates (partially).Tristan Gingold2019-11-042-48/+125
* synth-value: export get_bound_length.Tristan Gingold2019-11-041-0/+3
* ghdlmain: simplify code.Tristan Gingold2019-11-041-4/+1
* vhdl-scanner: handle 'synopsys' pragma.Tristan Gingold2019-11-043-16/+19
* ghdlmain: fix deallocation in response file handling.Tristan Gingold2019-11-041-0/+10
* netlists-expands: expand rol.Tristan Gingold2019-11-031-0/+30
* synth-oper: use build2_uresizeTristan Gingold2019-11-031-16/+2
* netlists-utils: add clog2Tristan Gingold2019-11-032-0/+8
* netlists-builders: add build2_uresize.Tristan Gingold2019-11-032-0/+31
* synth: fix multiport read memories (for issue #1000)Tristan Gingold2019-11-031-1/+3
* synth: cap max in synth_slice_suffixTristan Gingold2019-11-031-1/+8
* netlists-expands: rewrite generate_muxes.Tristan Gingold2019-11-031-24/+102
* netlists-expands: use a safe walk.Tristan Gingold2019-11-031-1/+3
* synth: add support for inout variable interfaces.Tristan Gingold2019-11-012-3/+4
* synth-values: handle value_const for is_equal.Tristan Gingold2019-11-011-0/+5
* synth: handle nested if generate statements.Tristan Gingold2019-11-012-21/+29
* netlits: fix memidx order.Tristan Gingold2019-11-012-39/+52
* netlists-dump: improve output.Tristan Gingold2019-11-011-10/+11
* netlists-expands: expand dyn_insertTristan Gingold2019-11-012-42/+174
* psl-nfa-utils: move active state in merge_state.Tristan Gingold2019-10-311-0/+5
* vhdl-prints: handle more constructs in psl vunit.Tristan Gingold2019-10-311-0/+5
* ghdlsynth_gates.h: regenerate.Tristan Gingold2019-10-311-0/+4
* synth: handle attributes in vunit.Tristan Gingold2019-10-301-1/+86
* netlists: add formal input gates.Tristan Gingold2019-10-303-0/+44
* vhdl: allow attributes in vunit declarations.Tristan Gingold2019-10-306-200/+216
* Add names for formal input gates/attributes.Tristan Gingold2019-10-302-1/+13
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