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authorTristan Gingold <tgingold@free.fr>2019-10-30 18:39:06 +0100
committerTristan Gingold <tgingold@free.fr>2019-10-30 18:39:06 +0100
commitbeadc8e7be3d5d58f6b76d405673642c58b23a30 (patch)
tree05f462afc62e5ee29a06213783aa8c34cb12af6b /src
parent500c7cf4c7d307cb51c309e6ebc9c5285e7c5f97 (diff)
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Add names for formal input gates/attributes.
Diffstat (limited to 'src')
-rw-r--r--src/std_names.adb5
-rw-r--r--src/std_names.ads9
2 files changed, 13 insertions, 1 deletions
diff --git a/src/std_names.adb b/src/std_names.adb
index d4722240c..aba33a9f6 100644
--- a/src/std_names.adb
+++ b/src/std_names.adb
@@ -654,6 +654,11 @@ package body Std_Names is
Def ("ceil", Name_Ceil);
Def ("log2", Name_Log2);
+ Def ("allconst", Name_Allconst);
+ Def ("allseq", Name_Allseq);
+ Def ("anyconst", Name_Anyconst);
+ Def ("anyseq", Name_Anyseq);
+
-- Verilog directives
Def ("define", Name_Define);
Def ("endif", Name_Endif);
diff --git a/src/std_names.ads b/src/std_names.ads
index 710c04814..4c560eac5 100644
--- a/src/std_names.ads
+++ b/src/std_names.ads
@@ -736,8 +736,15 @@ package Std_Names is
Name_Log2 : constant Name_Id := Name_First_Ieee + 034;
Name_Last_Ieee : constant Name_Id := Name_Log2;
+ Name_First_Synthesis : constant Name_Id := Name_Last_Ieee + 1;
+ Name_Allconst : constant Name_Id := Name_First_Synthesis + 000;
+ Name_Allseq : constant Name_Id := Name_First_Synthesis + 001;
+ Name_Anyconst : constant Name_Id := Name_First_Synthesis + 002;
+ Name_Anyseq : constant Name_Id := Name_First_Synthesis + 003;
+ Name_Last_Synthesis : constant Name_Id := Name_Anyseq;
+
-- Verilog Directives.
- Name_First_Directive : constant Name_Id := Name_Last_Ieee + 1;
+ Name_First_Directive : constant Name_Id := Name_Last_Synthesis + 1;
Name_Define : constant Name_Id := Name_First_Directive + 00;
Name_Endif : constant Name_Id := Name_First_Directive + 01;
Name_Ifdef : constant Name_Id := Name_First_Directive + 02;