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authorTristan Gingold <tgingold@free.fr>2019-11-03 07:38:22 +0100
committerTristan Gingold <tgingold@free.fr>2019-11-03 21:15:07 +0100
commit79c615e88dd652d7f2077ccdbef0487d74febd98 (patch)
tree0c4c29b44ec981622ff2d1cc4eabb8afe3892832 /src
parentce507d676a43233523fbdc1fc631b7a2043ce4e1 (diff)
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synth: cap max in synth_slice_suffix
Diffstat (limited to 'src')
-rw-r--r--src/synth/synth-expr.adb9
1 files changed, 8 insertions, 1 deletions
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb
index 628f1d589..02700859f 100644
--- a/src/synth/synth-expr.adb
+++ b/src/synth/synth-expr.adb
@@ -1209,6 +1209,7 @@ package body Synth.Expr is
Dir : Iir_Direction;
Step : Uns32;
Max : Uns32;
+ Inp_W : Width;
begin
Off := 0;
@@ -1260,16 +1261,22 @@ package body Synth.Expr is
Synth_Extract_Dyn_Suffix
(Name, Pfx_Bnd, Get_Net (Left), Get_Net (Right),
Inp, Step, Off, Wd);
+ Inp_W := Get_Width (Inp);
-- FIXME: convert range to offset.
+ -- Extract max from the range.
-- example: len=128 wd=8 step=8 => max=16
-- len=8 wd=4 step=1 => max=4
-- max so that max*step+wd <= len - off
-- max <= (len - off - wd) / step
Max := (Pfx_Bnd.Len - Off - Wd) / Step;
+ if Clog2 (Uns64 (Max)) > Natural (Inp_W) then
+ -- The width of Inp limits the max.
+ Max := 2**Natural (Inp_W) - 1;
+ end if;
Inp := Build_Memidx
(Get_Build (Syn_Inst),
Inp, Step * El_Wd, Max,
- Get_Width (Inp) + Width (Clog2 (Uns64 (Step * El_Wd))));
+ Inp_W + Width (Clog2 (Uns64 (Step * El_Wd))));
Wd := Wd * El_Wd;
end if;
end Synth_Slice_Suffix;