| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | synth: improve error recovery | Tristan Gingold | 2022-10-02 | 1 | -0/+3 |
| * | synth: detect division by 0, handle universal real/integer division | Tristan Gingold | 2022-10-02 | 1 | -3/+23 |
| * | synth-vhdl_stmts: handle passive process. Fix ghdl/ghdl-yosys-plugin#174 | Tristan Gingold | 2022-10-02 | 1 | -18/+204 |
| * | synth: avoid a crash on literal overflow | Tristan Gingold | 2022-10-01 | 1 | -1/+10 |
| * | synth: avoid on crash on overflow in ranges | Tristan Gingold | 2022-10-01 | 1 | -0/+8 |
| * | synth: improve handling of individual generic associations | Tristan Gingold | 2022-10-01 | 1 | -17/+22 |
| * | simul: finalize empty procedures | Tristan Gingold | 2022-10-01 | 1 | -9/+11 |
| * | simul: minor rewrite | Tristan Gingold | 2022-10-01 | 1 | -3/+2 |
| * | simul: finalize declarations of procedure calls | Tristan Gingold | 2022-10-01 | 2 | -0/+6 |
| * | synth: handle read for floats | Tristan Gingold | 2022-09-30 | 2 | -8/+24 |
| * | synth: handle float-float conversions | Tristan Gingold | 2022-09-30 | 1 | -3/+14 |
| * | simul: handle stable attribute | Tristan Gingold | 2022-09-30 | 2 | -5/+44 |
| * | synth: factorize code | Tristan Gingold | 2022-09-30 | 2 | -8/+9 |
| * | simul: create disconnections | Tristan Gingold | 2022-09-30 | 1 | -1/+42 |
| * | libraries.adb: do not set location of entity name of architecture. | Tristan Gingold | 2022-09-30 | 1 | -1/+0 |
| * | ortho/llvm6: handle llvm 15 (opaque pointers) | Tristan Gingold | 2022-09-29 | 1 | -39/+64 |
| * | simul: handle quiet attribute | Tristan Gingold | 2022-09-29 | 4 | -12/+88 |
| * | simul: factorize code, add sub_signal_type | Tristan Gingold | 2022-09-29 | 4 | -92/+73 |
| * | vhdl-canon: extract guard for signal assignment sensitivity | Tristan Gingold | 2022-09-29 | 1 | -1/+15 |
| * | simul: support guarded signal assignments (WIP) | Tristan Gingold | 2022-09-29 | 1 | -8/+79 |
| * | synth: handle guard signal in debugger | Tristan Gingold | 2022-09-28 | 3 | -57/+78 |
| * | simul: handle last_value attribute | Tristan Gingold | 2022-09-28 | 3 | -1/+31 |
| * | synth: handle guard signal in expressions | Tristan Gingold | 2022-09-28 | 2 | -0/+2 |
| * | simul: fix handling of labels in next/exit statements | Tristan Gingold | 2022-09-28 | 1 | -4/+13 |
| * | synth: handle null-range loops | Tristan Gingold | 2022-09-28 | 5 | -21/+40 |
| * | vhdl-sem: avoid a crash after error. Fix #2201 | Tristan Gingold | 2022-09-28 | 1 | -0/+1 |
| * | synth: handle names in record aggregate targets | Tristan Gingold | 2022-09-28 | 1 | -0/+12 |
| * | synth: handle array target aggregate | Tristan Gingold | 2022-09-27 | 1 | -2/+6 |
| * | synth: handle error on variable default value | Tristan Gingold | 2022-09-27 | 1 | -0/+5 |
| * | simul: handle null signal assignments | Tristan Gingold | 2022-09-27 | 1 | -12/+36 |
| * | synth-vhdl_eval: handle nor, nand | Tristan Gingold | 2022-09-26 | 1 | -0/+21 |
| * | simul-vhdl_elab: avoid a crash for null-range signals | Tristan Gingold | 2022-09-26 | 1 | -10/+14 |
| * | synth: handle attributes in configurations | Tristan Gingold | 2022-09-26 | 4 | -3/+16 |
| * | synth: improve error checks (type conversion, string literals) | Tristan Gingold | 2022-09-25 | 3 | -33/+37 |
| * | synth: rework error procedure, always pass the instance | Tristan Gingold | 2022-09-25 | 17 | -254/+406 |
| * | synth-vhdl_eval: handle vhdl-87 array array concatenation | Tristan Gingold | 2022-09-25 | 1 | -2/+31 |
| * | vhdl-sem_decls: handle protected type subtypes | Tristan Gingold | 2022-09-25 | 1 | -1/+4 |
| * | vhdl-sem_names: handle architecture bodies in sem_denoting_name | Tristan Gingold | 2022-09-25 | 1 | -1/+2 |
| * | synth-vhdl_stmts: fix missing newline in default assertion messages | Tristan Gingold | 2022-09-25 | 1 | -3/+3 |
| * | synth: handle default expression for IN variables in assocs | Tristan Gingold | 2022-09-25 | 1 | -4/+10 |
| * | synth: handle selected names in targets | Tristan Gingold | 2022-09-25 | 1 | -1/+2 |
| * | synth-vhdl_eval: handle null-null in array concatenations | Tristan Gingold | 2022-09-25 | 1 | -0/+6 |
| * | simul: gather disconnection specifications, create guard signal | Tristan Gingold | 2022-09-25 | 4 | -36/+194 |
| * | synth: ignore groups and group templates | Tristan Gingold | 2022-09-25 | 3 | -1/+15 |
| * | grt: do not initialial GUARD signals on creation. | Tristan Gingold | 2022-09-25 | 1 | -1/+4 |
| * | synth: handle attribute names | Tristan Gingold | 2022-09-25 | 1 | -13/+16 |
| * | synth: handle individual subprogram associations for expressions | Tristan Gingold | 2022-09-25 | 1 | -55/+61 |
| * | simul: handle empty procedures | Tristan Gingold | 2022-09-25 | 1 | -1/+9 |
| * | synth: rework association conversions | Tristan Gingold | 2022-09-25 | 3 | -62/+75 |
| * | synth-vhdl_stmts: rework for subprogram associations (WIP) | Tristan Gingold | 2022-09-25 | 1 | -57/+36 |
