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* libghdl: also add synthesis part. For #884Tristan Gingold2019-08-136-52/+56
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* synth: build_header was replaced by a Makefile target.Tristan Gingold2019-08-131-8/+0
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* libghdl: preliminary work to also support synth.Tristan Gingold2019-08-132-4/+9
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* vhdl: improve reprint of inertial association.Tristan Gingold2019-08-116-181/+206
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* vhdl-sem: fix minor thinko for sem_insert_anonymous_signal.Tristan Gingold2019-08-111-1/+24
| | | | Fix #885
* vhdl: avoid crash on incorrect unit name.Tristan Gingold2019-08-102-6/+36
| | | | Fix #886
* vhdl: handle subtype indication (with range) in discrete_range.Tristan Gingold2019-08-107-63/+105
| | | | For #877
* synth: add comments.Tristan Gingold2019-08-091-1/+9
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* vhdl: remove unused Get/Set_Choice_Order.Tristan Gingold2019-08-095-304/+247
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* synth: fix crash when assignment target is an aggregate.Tristan Gingold2019-08-081-5/+7
| | | | For tgingold/ghdlsynth-beta#26
* vhdl: remove -Whides warnings for processes without a label.Tristan Gingold2019-08-081-0/+9
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* synth: handle 1 bit integer in disp_vhdl, fix range in synth-expr.Tristan Gingold2019-08-082-4/+13
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* vhdl: remove severity from cover, report and severity from assume.Tristan Gingold2019-08-0811-142/+160
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* vhdl-nodes: gather PSL nodes, regenerate nodes_meta.Tristan Gingold2019-08-072-125/+91
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* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-0730-141/+334
| | | | | | | | | | | | | | | | | | | | | | | | | | * vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code
* vhdl: allow discrete subtype indication for discrete_range.Tristan Gingold2019-08-065-45/+53
| | | | For #877
* vhdl: for time resolution, do not consider unit name from textio body.Tristan Gingold2019-08-062-10/+38
| | | | For #881
* synth: improve support of vhdl08. Fix #882Tristan Gingold2019-08-052-5/+22
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* synth: add asserts in synth-valuesTristan Gingold2019-08-051-0/+5
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* synth: handle subtype conversions.Tristan Gingold2019-08-055-73/+154
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* synth: handle signed conversions in disp_vhdl.Tristan Gingold2019-08-051-2/+6
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* synth: preliminary support of integer literals.Tristan Gingold2019-08-022-18/+67
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* synth: add a debug procedure.Tristan Gingold2019-08-022-0/+22
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* synth: improve error message for multiple assignments.Tristan Gingold2019-08-021-4/+20
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* synth: handle signed integer comparisons (#878)Pepijn de Vos2019-08-013-0/+43
| | | | | | | | | | * comparisons with integer literals * display signed comparison nicely * revert literal size changes * properly display signed values
* synth: handle partial assignments in a process (WIP).Tristan Gingold2019-08-011-18/+75
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* synth: refactoring in inference/environment.Tristan Gingold2019-08-013-7/+13
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* synth: refactor inference, add comment, strengthen check.Tristan Gingold2019-08-014-31/+62
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* synth: refactoring in synth-inference.Tristan Gingold2019-07-311-129/+137
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* synth: add location on monadic operators.Tristan Gingold2019-07-311-7/+10
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* synth: regenerate ghdlsynth_gates.hTristan Gingold2019-07-311-3/+4
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* synth: fix a crash in instantiation.Tristan Gingold2019-07-312-8/+9
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* synth: slightly improve output for indexes.Tristan Gingold2019-07-301-3/+7
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* synth: adjust output for dyn_insert, add dpram2 test.Tristan Gingold2019-07-301-2/+2
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* synth: fixes for indexed names.Tristan Gingold2019-07-303-3/+13
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* synth: rework indexed names.Tristan Gingold2019-07-304-101/+106
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* synth: handle more conversions in disp_vhdlTristan Gingold2019-07-291-1/+44
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* synth: add support for memories.Tristan Gingold2019-07-2915-152/+445
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* synth: remove extract_bound (trivial).Tristan Gingold2019-07-285-15/+6
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* synth: unconstrained arrays.Tristan Gingold2019-07-285-17/+71
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* synth: preliminary support of dynamic indexing.Tristan Gingold2019-07-2813-740/+956
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* vhdl: linearize analyze and evaluation of concat operators.Tristan Gingold2019-07-265-360/+647
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* synth: rework range.Tristan Gingold2019-07-265-48/+52
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* synth: preliminary support of integer subtypes.Tristan Gingold2019-07-268-42/+68
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* synth: handle array aggregate.Tristan Gingold2019-07-262-27/+32
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* synth: handle bit.Tristan Gingold2019-07-253-4/+11
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* synth: array inequality, integer in choices.Tristan Gingold2019-07-252-0/+11
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* vhdl+synth: recognize /= to std_logic_unsigned.Tristan Gingold2019-07-253-1/+16
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* vhdl: handle (discard) more pragmas.Tristan Gingold2019-07-253-1/+19
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* synth: save and display locations for instances.Tristan Gingold2019-07-258-66/+247
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