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* ghdldrv: extract trans_link from ghdlrunTristan Gingold2023-01-213-459/+499
* elab-vhdl_debug: add 'info lib' and 'info units'Tristan Gingold2023-01-211-0/+78
* elab-vhdl_debug: disp generate block declarationsTristan Gingold2023-01-201-2/+4
* elab-vhdl_debug: disp process declarationsTristan Gingold2023-01-201-0/+10
* synth: create sub-instace for processesTristan Gingold2023-01-205-6/+18
* elab: Rename Get/Set_Info to Get/Set_AnnTristan Gingold2023-01-204-58/+59
* synth: add partial support of foreign subprogramsTristan Gingold2023-01-206-2/+363
* std_names: add more AMS namesTristan Gingold2023-01-182-1/+40
* simul: handle PSL endpointsTristan Gingold2023-01-184-10/+38
* simul: fix last_value for post vhdl 87Tristan Gingold2023-01-182-103/+145
* synth-vhdl_eval: add an overflow checkTristan Gingold2023-01-161-2/+6
* synth: emit an error message on foreign subprogram callsTristan Gingold2023-01-161-0/+11
* ghdlsimul: check foreign subprogramsTristan Gingold2023-01-161-3/+4
* vhdl: refactoring - remove trans_be, mainly added to vhdl-back_endTristan Gingold2023-01-169-274/+266
* synth: handle invididual assoc with unbounded formalsTristan Gingold2023-01-161-6/+130
* simul: disable --trace-signalsTristan Gingold2023-01-151-0/+4
* synth: avoid a crash on instantiationTristan Gingold2023-01-151-4/+19
* vhdl-sem.adb: also check elaboration status within package bodiesTristan Gingold2023-01-151-6/+19
* synth: avoid a crash on use before elaborationTristan Gingold2023-01-151-8/+16
* synth: add Debug_Backtrace debug procedureTristan Gingold2023-01-152-0/+19
* vhdl: add a warning to detect use before elaborationTristan Gingold2023-01-158-5/+99
* vhdl: add Get/Set_Elaboration_FlagTristan Gingold2023-01-144-265/+326
* synth: more refactoringTristan Gingold2023-01-145-40/+40
* synth: improve error propagation on slicesTristan Gingold2023-01-145-9/+31
* synth-vhdl_stmts: introduce synth_individual_formalTristan Gingold2023-01-141-18/+107
* synth-vhdl_stmts: refactoringTristan Gingold2023-01-141-103/+131
* elab-vhdl_types(synth_record_type_definition): create unbounded recordTristan Gingold2023-01-141-3/+8
* elab-vhdl_debug: add option /t to print result typeTristan Gingold2023-01-141-5/+6
* synth-vhdl_eval: remove useless type unsharing for concatTristan Gingold2023-01-141-12/+4
* synth: handle protected functions in conversion functionsTristan Gingold2023-01-123-8/+17
* simul: handle PSL abortsTristan Gingold2023-01-123-0/+71
* synth: improve handling of 2008 aggregatesTristan Gingold2023-01-121-27/+142
* elab-vhdl_values-debug: improve output for array unboundedTristan Gingold2023-01-121-14/+21
* ghdlsimul: handle automatic time resolutionTristan Gingold2023-01-121-12/+17
* synth: handle generic mapped interface packageTristan Gingold2023-01-121-5/+17
* vhdl-sem_assocs(rewrite_non_object_association): set flagTristan Gingold2023-01-121-0/+1
* vhdl: clear associated_type in Sem_Generic_Association_ChainTristan Gingold2023-01-125-9/+90
* elab-vhdl_annotations(annotate_interface_list_subtype): adjustTristan Gingold2023-01-121-3/+15
* simul: fix handling of drivers/sensitivity within processesTristan Gingold2023-01-123-21/+25
* synth: fix handle of protected type bodies within instantiated packages.Tristan Gingold2023-01-123-3/+30
* elab-vhdl_types: improve handling of record subtypesTristan Gingold2023-01-122-18/+27
* ghdl_simul: add commands to use libghdlTristan Gingold2023-01-121-0/+2
* synth: handle operator as conversion functionTristan Gingold2023-01-121-1/+13
* vhdl-sem_names: finish prefix of element attribute namesTristan Gingold2023-01-121-22/+32
* synth: report values in bound errorsTristan Gingold2023-01-122-9/+40
* synth: use same wording for direction mismatch as simulationTristan Gingold2023-01-121-1/+2
* synth-vhdl_eval: handle to_X01 for bit to std_ulogic.Tristan Gingold2023-01-113-0/+39
* synth: handle entity attributesTristan Gingold2023-01-111-2/+18
* synth: handle universal r*i and i*r mul, physical mod.Tristan Gingold2023-01-111-1/+9
* synth: handle element attributeTristan Gingold2023-01-114-9/+39
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