aboutsummaryrefslogtreecommitdiffstats
path: root/src
Commit message (Expand)AuthorAgeFilesLines
...
* simul: finalize declarations of procedure callsTristan Gingold2022-10-012-0/+6
* synth: handle read for floatsTristan Gingold2022-09-302-8/+24
* synth: handle float-float conversionsTristan Gingold2022-09-301-3/+14
* simul: handle stable attributeTristan Gingold2022-09-302-5/+44
* synth: factorize codeTristan Gingold2022-09-302-8/+9
* simul: create disconnectionsTristan Gingold2022-09-301-1/+42
* libraries.adb: do not set location of entity name of architecture.Tristan Gingold2022-09-301-1/+0
* ortho/llvm6: handle llvm 15 (opaque pointers)Tristan Gingold2022-09-291-39/+64
* simul: handle quiet attributeTristan Gingold2022-09-294-12/+88
* simul: factorize code, add sub_signal_typeTristan Gingold2022-09-294-92/+73
* vhdl-canon: extract guard for signal assignment sensitivityTristan Gingold2022-09-291-1/+15
* simul: support guarded signal assignments (WIP)Tristan Gingold2022-09-291-8/+79
* synth: handle guard signal in debuggerTristan Gingold2022-09-283-57/+78
* simul: handle last_value attributeTristan Gingold2022-09-283-1/+31
* synth: handle guard signal in expressionsTristan Gingold2022-09-282-0/+2
* simul: fix handling of labels in next/exit statementsTristan Gingold2022-09-281-4/+13
* synth: handle null-range loopsTristan Gingold2022-09-285-21/+40
* vhdl-sem: avoid a crash after error. Fix #2201Tristan Gingold2022-09-281-0/+1
* synth: handle names in record aggregate targetsTristan Gingold2022-09-281-0/+12
* synth: handle array target aggregateTristan Gingold2022-09-271-2/+6
* synth: handle error on variable default valueTristan Gingold2022-09-271-0/+5
* simul: handle null signal assignmentsTristan Gingold2022-09-271-12/+36
* synth-vhdl_eval: handle nor, nandTristan Gingold2022-09-261-0/+21
* simul-vhdl_elab: avoid a crash for null-range signalsTristan Gingold2022-09-261-10/+14
* synth: handle attributes in configurationsTristan Gingold2022-09-264-3/+16
* synth: improve error checks (type conversion, string literals)Tristan Gingold2022-09-253-33/+37
* synth: rework error procedure, always pass the instanceTristan Gingold2022-09-2517-254/+406
* synth-vhdl_eval: handle vhdl-87 array array concatenationTristan Gingold2022-09-251-2/+31
* vhdl-sem_decls: handle protected type subtypesTristan Gingold2022-09-251-1/+4
* vhdl-sem_names: handle architecture bodies in sem_denoting_nameTristan Gingold2022-09-251-1/+2
* synth-vhdl_stmts: fix missing newline in default assertion messagesTristan Gingold2022-09-251-3/+3
* synth: handle default expression for IN variables in assocsTristan Gingold2022-09-251-4/+10
* synth: handle selected names in targetsTristan Gingold2022-09-251-1/+2
* synth-vhdl_eval: handle null-null in array concatenationsTristan Gingold2022-09-251-0/+6
* simul: gather disconnection specifications, create guard signalTristan Gingold2022-09-254-36/+194
* synth: ignore groups and group templatesTristan Gingold2022-09-253-1/+15
* grt: do not initialial GUARD signals on creation.Tristan Gingold2022-09-251-1/+4
* synth: handle attribute namesTristan Gingold2022-09-251-13/+16
* synth: handle individual subprogram associations for expressionsTristan Gingold2022-09-251-55/+61
* simul: handle empty proceduresTristan Gingold2022-09-251-1/+9
* synth: rework association conversionsTristan Gingold2022-09-253-62/+75
* synth-vhdl_stmts: rework for subprogram associations (WIP)Tristan Gingold2022-09-251-57/+36
* synth-vhdl_stmts: support of individual paramater associations (WIP)Tristan Gingold2022-09-252-106/+238
* simul: reuse drivers extraction from elaborationTristan Gingold2022-09-252-74/+26
* synth-vhdl_stmts: refactore synth_subprogram_associationsTristan Gingold2022-09-251-49/+52
* synth-vhdl_stmts: refactoreTristan Gingold2022-09-251-23/+32
* synth-vhdl_stmts: refactoringTristan Gingold2022-09-251-189/+208
* synth-vhdl_stmts: rework in progress of subprogram associationsTristan Gingold2022-09-251-108/+115
* synth-vhdl_insts: move pragma unreferencedTristan Gingold2022-09-211-1/+2
* synth: simplify elab-vhdl_annotationsTristan Gingold2022-09-192-51/+3
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-24 17:51:02 +0000