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Author
Age
Files
Lines
*
synth: remove extract_bound (trivial).
Tristan Gingold
2019-07-28
5
-15
/
+6
*
synth: unconstrained arrays.
Tristan Gingold
2019-07-28
5
-17
/
+71
*
synth: preliminary support of dynamic indexing.
Tristan Gingold
2019-07-28
13
-740
/
+956
*
vhdl: linearize analyze and evaluation of concat operators.
Tristan Gingold
2019-07-26
5
-360
/
+647
*
synth: rework range.
Tristan Gingold
2019-07-26
5
-48
/
+52
*
synth: preliminary support of integer subtypes.
Tristan Gingold
2019-07-26
8
-42
/
+68
*
synth: handle array aggregate.
Tristan Gingold
2019-07-26
2
-27
/
+32
*
synth: handle bit.
Tristan Gingold
2019-07-25
3
-4
/
+11
*
synth: array inequality, integer in choices.
Tristan Gingold
2019-07-25
2
-0
/
+11
*
vhdl+synth: recognize /= to std_logic_unsigned.
Tristan Gingold
2019-07-25
3
-1
/
+16
*
vhdl: handle (discard) more pragmas.
Tristan Gingold
2019-07-25
3
-1
/
+19
*
synth: save and display locations for instances.
Tristan Gingold
2019-07-25
8
-66
/
+247
*
synth: fix incorrect slice in disp_vhdl for Insert.
Tristan Gingold
2019-07-25
1
-6
/
+1
*
vhdl annotations: fix annotation of type in interface list.
Tristan Gingold
2019-07-24
1
-0
/
+1
*
synth: fix bad ordering in case statement.
Tristan Gingold
2019-07-24
1
-2
/
+3
*
synth: do not consider (unrecognized) ieee functions as user functions.
Tristan Gingold
2019-07-24
1
-0
/
+19
*
synth: enable handling of pragma translate_on/off.
Tristan Gingold
2019-07-24
1
-0
/
+3
*
vhdl scanner: handle pragma translate_on/translate_off.
Tristan Gingold
2019-07-24
5
-5
/
+109
*
synth: handle resize.
Tristan Gingold
2019-07-24
1
-0
/
+15
*
synth: handle record type declarations.
Tristan Gingold
2019-07-24
1
-1
/
+11
*
vhdl: recognize resize function.
Tristan Gingold
2019-07-24
4
-3
/
+43
*
synth: fix slice/indexed assignment that partially override previous assign.
Tristan Gingold
2019-07-23
1
-5
/
+8
*
synth: add more operators.
Tristan Gingold
2019-07-23
1
-1
/
+34
*
synth: fix to_unsigned.
Tristan Gingold
2019-07-23
1
-2
/
+2
*
synth: use original entity to display netlist.
Tristan Gingold
2019-07-23
7
-22
/
+314
*
vhdl-prints: improve output for ports/generics.
Tristan Gingold
2019-07-22
1
-5
/
+27
*
synth: remove bounds (unused) for ports.
Tristan Gingold
2019-07-22
4
-13
/
+4
*
ghdlsynth: preliminary work for wrapped generation.
Tristan Gingold
2019-07-22
1
-1
/
+8
*
synth: minor refactoring in netlists.disp_vhdl
Tristan Gingold
2019-07-22
2
-47
/
+54
*
synth: minor rework.
Tristan Gingold
2019-07-22
3
-10
/
+37
*
synth: rework names.
Tristan Gingold
2019-07-22
6
-24
/
+25
*
add port width utility function for yosys (#876)
Pepijn de Vos
2019-07-21
4
-0
/
+18
*
synth: improve output (id_extract).
Tristan Gingold
2019-07-20
1
-6
/
+12
*
synth: improve output (for id_insert).
Tristan Gingold
2019-07-20
1
-11
/
+18
*
synth: add support for concurrent selected signal assignment.
Tristan Gingold
2019-07-20
1
-2
/
+138
*
synth: support index of a constant.
Tristan Gingold
2019-07-20
1
-0
/
+4
*
synth: initial support for for-generate statement.
Tristan Gingold
2019-07-20
3
-34
/
+97
*
synth: add and merge phi within a function.
Tristan Gingold
2019-07-20
1
-0
/
+5
*
synth: fix aggregate vectorize direction.
Tristan Gingold
2019-07-20
2
-5
/
+6
*
synth: add concatn gate
Tristan Gingold
2019-07-19
9
-32
/
+126
*
synth: finalize concurrent assignments (WIP).
Tristan Gingold
2019-07-19
6
-33
/
+342
*
synth: add const_z gate.
Tristan Gingold
2019-07-19
4
-3
/
+33
*
errorout: handle %v for values.
Tristan Gingold
2019-07-19
2
-1
/
+36
*
synth: make more types private.
Tristan Gingold
2019-07-17
2
-35
/
+48
*
synth: make type Wire_Id_Record private.
Tristan Gingold
2019-07-17
7
-44
/
+74
*
synth: renaming of Assign to Seq_Assign.
Tristan Gingold
2019-07-17
6
-79
/
+82
*
synth: add comments.
Tristan Gingold
2019-07-17
2
-0
/
+2
*
vhdl: add a comment.
Tristan Gingold
2019-07-16
1
-0
/
+3
*
synth: add > and >= operators (#870)
Pepijn de Vos
2019-07-16
6
-25
/
+118
*
vhdl: avoid a crash on no matching operator error.
Tristan Gingold
2019-07-15
1
-1
/
+7
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