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* ghdlsynth: check top entity can be a top entity.Tristan Gingold2019-07-145-23/+41
* vhdl: refactoring: remove configure function with string access.Tristan Gingold2019-07-148-105/+95
* vhdl: set location on reference to the anonymous signal declaration.Tristan Gingold2019-07-141-0/+1
* ghdlsynth: automatically find top entity if not specified.Tristan Gingold2019-07-141-8/+33
* vhdl: fixes in find_top_entity (handle for-generate, remove early return)Tristan Gingold2019-07-142-5/+27
* synth: handle anonymous signals.Tristan Gingold2019-07-141-0/+3
* synth: handle black boxes.Tristan Gingold2019-07-133-47/+108
* synth: handle simple component instances.Tristan Gingold2019-07-131-36/+256
* vhdl: cleanup in clear_instantiation_configuration.Tristan Gingold2019-07-134-70/+23
* simul-elaboration: rewrite assertion.Tristan Gingold2019-07-131-3/+3
* vhdl-configuration: improve error message.Tristan Gingold2019-07-111-1/+1
* vhdl: minor reformating.Tristan Gingold2019-07-112-8/+5
* synth: set flag_elaborate.Tristan Gingold2019-07-112-1/+3
* vhdl-sem_lib: save and restore nbr_errors inTristan Gingold2019-07-111-0/+10
* libghdl: import Free_Dependence_List.Tristan Gingold2019-07-112-0/+4
* vhdl-nodes: add commentsTristan Gingold2019-07-111-0/+16
* synth_top_entity: pass config + minor cleanup.Tristan Gingold2019-07-113-13/+7
* synth-insts: minor cleanup.Tristan Gingold2019-07-111-7/+0
* synth: do not crash on use of std_logic_1164 2008.Tristan Gingold2019-07-102-12/+10
* synth: add synth_top_entity.Tristan Gingold2019-07-103-221/+96
* synth: add Id_Port gate to improve display.Tristan Gingold2019-07-105-29/+73
* synth: display instances in reverse order.Tristan Gingold2019-07-102-10/+41
* synth: handle instantiation (WIP)Tristan Gingold2019-07-1011-48/+587
* vhdl: improve an error message.Tristan Gingold2019-07-101-1/+1
* vhdl-sem_lib: Load_Parse_Design_Unit: ignore checksum ifTristan Gingold2019-07-091-3/+6
* vhdl-sem_lib: free_dependencies: only free entity aspect.Tristan Gingold2019-07-091-3/+19
* libghdl: automatically set the prefix from shared libraryTristan Gingold2019-07-093-1/+9
* ghdllocal: correctly disp GHDL_PREFIX in --disp-config.Tristan Gingold2019-07-093-8/+8
* vhdl: report an error in case of missing binding indication in config spec.Tristan Gingold2019-07-091-11/+21
* synthesis: add Node instead of Iir.Tristan Gingold2019-07-081-10/+10
* vhdl simul-elaboration: minor rewrite.Tristan Gingold2019-07-081-3/+1
* synth-environement: add comments.Tristan Gingold2019-07-082-3/+5
* synth: handle simple user function calls.Tristan Gingold2019-07-066-18/+89
* synth: support top-level generics.Tristan Gingold2019-07-062-0/+23
* configure: add --enable-synth (off by default).Tristan Gingold2019-07-064-4/+27
* ghdlsynth.h: follow convention, add comments.Tristan Gingold2019-07-041-13/+16
* vhdl-annotations: partial revert of previous patch forTristan Gingold2019-07-042-1/+12
* synth: use future states for PSL restrict directive.Tristan Gingold2019-07-041-5/+8
* synth: handle some "/=".Tristan Gingold2019-07-042-0/+23
* libghdlsynth: catch all exceptions.Tristan Gingold2019-07-041-0/+3
* vhdl/translate: reindent.Tristan Gingold2019-07-041-1/+1
* synth: handle PSL restrict directive (WIP).Tristan Gingold2019-07-042-1/+111
* synth: add concat_array function.Tristan Gingold2019-07-042-36/+52
* netlists-disp_vhdl: display initial value of idff.Tristan Gingold2019-07-041-19/+32
* netlists: export new_internal_name.Tristan Gingold2019-07-041-4/+10
* netlists: allow to build idff without a connected D.Tristan Gingold2019-07-042-3/+6
* netlists: add reduce_or/reduce_and gates.Tristan Gingold2019-07-044-0/+36
* netlists: add assume gate.Tristan Gingold2019-07-045-3/+29
* libghdlsynth: decode options.Tristan Gingold2019-07-043-76/+104
* vhdl: rename Cover_Statement to Cover_Directive.Tristan Gingold2019-07-0417-57/+57
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