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| author | Tristan Gingold <tgingold@free.fr> | 2019-07-12 19:42:48 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-07-13 08:03:52 +0200 |
| commit | 61179df112a8a039dbf234eeb9dbfa7327a1f62c (patch) | |
| tree | c8cb0d149d9c5cb116ca9b01736c69d904a011f2 /src | |
| parent | 947e49c40fc96eede34af48728899205178bd40f (diff) | |
| download | ghdl-61179df112a8a039dbf234eeb9dbfa7327a1f62c.tar.gz ghdl-61179df112a8a039dbf234eeb9dbfa7327a1f62c.tar.bz2 ghdl-61179df112a8a039dbf234eeb9dbfa7327a1f62c.zip | |
simul-elaboration: rewrite assertion.
Diffstat (limited to 'src')
| -rw-r--r-- | src/vhdl/simulate/simul-elaboration.adb | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb index b4f690ab4..61048392b 100644 --- a/src/vhdl/simulate/simul-elaboration.adb +++ b/src/vhdl/simulate/simul-elaboration.adb @@ -2304,9 +2304,9 @@ package body Simul.Elaboration is El : Iir; Info : Sim_Info_Acc; begin - if List = Iir_Flist_All or else List = Iir_Flist_Others then - raise Internal_Error; - end if; + -- The list has been expanded by canon. + pragma Assert (List /= Iir_Flist_All + and then List /= Iir_Flist_Others); for I in Flist_First .. Flist_Last (List) loop El := Get_Nth_Element (List, I); Info := Get_Info (Get_Named_Entity (El)); |