vhdl-annotations: partial revert of previous patch for

2 files changed, 12 insertions, 1 deletions

diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb
index 688f67a4e..e819ac116 100644
--- a/src/synth/synth-decls.adb
+++ b/src/synth/synth-decls.adb
@@ -33,7 +33,6 @@ with Vhdl.Annotations; use Vhdl.Annotations;
 package body Synth.Decls is
    procedure Synth_Anonymous_Subtype_Indication
      (Syn_Inst : Synth_Instance_Acc; Atype : Node);
-   pragma Unreferenced (Synth_Anonymous_Subtype_Indication);
 
    procedure Create_Var_Wire
      (Syn_Inst : Synth_Instance_Acc; Decl : Iir; Init : Value_Acc)
@@ -114,6 +113,8 @@ package body Synth.Decls is
             --  The elaboration of an index constraint consists of the
             --  declaration of each of the discrete ranges in the index
             --  constraint in some order that is not defined by the language.
+            Synth_Anonymous_Subtype_Indication
+              (Syn_Inst, Get_Element_Subtype (Atype));
             declare
                St_Indexes : constant Iir_Flist :=
                  Get_Index_Subtype_List (Atype);
diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb
index 074ea4f15..1d9792948 100644
--- a/src/vhdl/vhdl-annotations.adb
+++ b/src/vhdl/vhdl-annotations.adb
@@ -359,6 +359,16 @@ package body Vhdl.Annotations is
             Annotate_Anonymous_Type_Definition (Block_Info, El);
 
          when Iir_Kind_Array_Subtype_Definition =>
+            declare
+               El_Type : constant Iir := Get_Element_Subtype (Def);
+               Bel_Type : constant Iir :=
+                 Get_Element_Subtype (Get_Base_Type (Def));
+            begin
+               if El_Type /= Bel_Type then
+                  Annotate_Anonymous_Type_Definition
+                    (Block_Info, Get_Element_Subtype (Def));
+               end if;
+            end;
             if Flag_Synthesis then
                --  For the bounds.
                Create_Object_Info (Block_Info, Def);