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* vhdl: avoid error storms in assertionsTristan Gingold2023-02-021-1/+3
* vhdl: add iir_kind_psl_boolean_parameter node. For #2178Tristan Gingold2022-08-151-2/+8
* vhdl-sem_psl: analyze strong propertiesTristan Gingold2022-07-021-1/+2
* synth: handle type declarations in vunit. Fix #2034Tristan Gingold2022-04-131-0/+1
* vhdl-sem_psl.adb: don't crash on overload in HDL expr. Fix #1979Tristan Gingold2022-02-241-2/+12
* vhdl/psl: handle PSL inherit spec. For #1899Tristan Gingold2021-11-051-26/+67
* synth: Support alias declarations in vunittmeissner2021-11-021-1/+3
* synth: add support for sequence instance in vunit. Fix #1889Tristan Gingold2021-10-131-0/+2
* vhdl and psl: parse sync_abort and async_abort. For #1654Tristan Gingold2021-08-301-1/+3
* vhdl: also allow type and subtype declarations in vunit. For #1724Tristan Gingold2021-04-151-0/+2
* vhdl: handle constant declarations in PSL vunit. Fix #1724Tristan Gingold2021-04-151-0/+1
* vhdl-sem_psl.adb: can also extract clock from SERE. For #1721Tristan Gingold2021-04-131-1/+5
* vhdl-sem_psl.adb: handle goto/equal repeated sequence. For #1708Tristan Gingold2021-04-051-8/+20
* psl: prefix of goto/non-consecutive repetition is a bool. Fix #1708Tristan Gingold2021-04-031-8/+12
* src: Handle also Equal Repeat and Goto repeat sequences. Keep TODO about chec...Ondrej Ille2021-03-281-5/+5
* src: Un-handle Equal and Goto repeat sequences in sem_property. Some form of ...Ondrej Ille2021-03-281-10/+5
* psl, vhdl: Extend semantic pass for PSL to allow "assert never <Sequence>" wi...Ondrej Ille2021-03-281-0/+10
* vhdl-sem_psl: factorize code for onehot/onehot0 and stable/fell/rose.Tristan Gingold2021-02-091-89/+6
* Add support for PSL onehot/onehot0 functions (#1633)T. Meissner2021-02-091-0/+32
* update license headersumarcor2021-01-141-11/+9
* vhdl-sem_psl: fix crash in case of error in assert statement. Fix #1480Tristan Gingold2020-09-281-2/+5
* vhdl: add wildcard_psl_boolean. For #1387Tristan Gingold2020-07-021-70/+73
* vhdl-sem_psl: avoid a crash in synth on incorrect clock.Tristan Gingold2020-06-301-0/+2
* vhdl psl: add support for equivalence operator. Fix #1371Tristan Gingold2020-06-161-4/+7
* vhdl: analyze and synth concurrent statements in vunit. Fix #1366Tristan Gingold2020-06-121-7/+12
* Synthesis of PSL built-in fell() function.tmeissner2020-06-071-0/+35
* Synthesis of PSL built-in rose() function.tmeissner2020-06-061-1/+36
* Synthesis of PSL stable() function.tmeissner2020-06-061-0/+35
* Synthesis of PSL prev function.Tristan Gingold2020-06-021-0/+60
* vhdl-sem_psl: handle equal/goto repeat seq. Fix #1321Tristan Gingold2020-05-181-1/+3
* vhdl-sem_psl: handle next_event_a and next_event_e. Fix #1292Tristan Gingold2020-05-091-0/+5
* Add handling of N_Next_E in PSL semantic passtmeissner2020-05-081-1/+1
* psl: keep locations.Tristan Gingold2020-04-261-4/+6
* psl: keep denoting names in the PSL ast.Tristan Gingold2020-03-131-10/+24
* vhdl: allow attributes in vunit declarations.Tristan Gingold2019-10-301-1/+3
* vhdl: extract sem_concurrent_statement, to handle hdl stmt in vunits.Tristan Gingold2019-10-251-0/+5
* vhdl-sem_psl: analyze some declarations.Tristan Gingold2019-10-231-0/+18
* vhdl: check cover/restrict is followed by a sequence.Tristan Gingold2019-10-161-0/+14
* vhdl: handle cover and restrict within vunit.Tristan Gingold2019-10-151-0/+4
* vhdl: handle architecture in verification unit hierarchical name.Tristan Gingold2019-08-201-7/+37
* vhdl: handle assume in verification units.Tristan Gingold2019-08-201-0/+2
* vhdl: parse verification unit (WIP).Tristan Gingold2019-08-171-3/+82
* vhdl: remove severity from cover, report and severity from assume.Tristan Gingold2019-08-081-18/+9
* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-071-3/+22
* vhdl: rename Cover_Statement to Cover_Directive.Tristan Gingold2019-07-041-2/+2
* vhdl: parse and analyze restrict directive.Tristan Gingold2019-07-041-0/+15
* vhdl: renames disp_vhdl to printsTristan Gingold2019-05-301-67/+69
* psl: can keep parenthesis during parse.Tristan Gingold2019-05-241-23/+70
* errorout: add messages group instead of continuation.Tristan Gingold2019-05-121-2/+4
* vhdl: decouple errorouts a bit more.Tristan Gingold2019-05-101-1/+0
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