vhdl: remove severity from cover, report and severity from assume.

1 files changed, 9 insertions, 18 deletions

diff --git a/src/vhdl/vhdl-sem_psl.adb b/src/vhdl/vhdl-sem_psl.adb
index 671c59c27..df0c1d8a1 100644
--- a/src/vhdl/vhdl-sem_psl.adb
+++ b/src/vhdl/vhdl-sem_psl.adb
@@ -736,9 +736,6 @@ package body Vhdl.Sem_Psl is
    is
       Prop : PSL_Node;
    begin
-      --  Sem report and severity expressions.
-      Sem_Report_Statement (Stmt);
-
       Prop := Get_Psl_Property (Stmt);
       Prop := Sem_Property (Prop, True);
       Set_Psl_Property (Stmt, Prop);
@@ -751,13 +748,10 @@ package body Vhdl.Sem_Psl is
       PSL.Subsets.Check_Simple (Prop);
    end Sem_Psl_Assume_Directive;
 
-   procedure Sem_Psl_Cover_Directive (Stmt : Iir)
+   procedure Sem_Psl_Sequence (Stmt : Iir)
    is
       Seq : PSL_Node;
    begin
-      --  Sem report and severity expressions.
-      Sem_Report_Statement (Stmt);
-
       Seq := Get_Psl_Sequence (Stmt);
       Seq := Sem_Sequence (Seq);
 
@@ -767,21 +761,18 @@ package body Vhdl.Sem_Psl is
 
       --  Check simple subset restrictions.
       PSL.Subsets.Check_Simple (Seq);
-   end Sem_Psl_Cover_Directive;
+   end Sem_Psl_Sequence;
 
-   procedure Sem_Psl_Restrict_Directive (Stmt : Iir)
-   is
-      Seq : PSL_Node;
+   procedure Sem_Psl_Cover_Directive (Stmt : Iir) is
    begin
-      Seq := Get_Psl_Sequence (Stmt);
-      Seq := Sem_Sequence (Seq);
+      Sem_Report_Expression (Stmt);
 
-      --  Properties must be clocked.
-      Sem_Psl_Directive_Clock (Stmt, Seq);
-      Set_Psl_Sequence (Stmt, Seq);
+      Sem_Psl_Sequence (Stmt);
+   end Sem_Psl_Cover_Directive;
 
-      --  Check simple subset restrictions.
-      PSL.Subsets.Check_Simple (Seq);
+   procedure Sem_Psl_Restrict_Directive (Stmt : Iir) is
+   begin
+      Sem_Psl_Sequence (Stmt);
    end Sem_Psl_Restrict_Directive;
 
    procedure Sem_Psl_Default_Clock (Stmt : Iir)