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vhdl-nodes.ads
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Author
Age
Files
Lines
*
synth: do not add info for element subtype (except for arrays).
Tristan Gingold
2022-04-05
1
-0
/
+1
*
vhdl: parse return identifier (v19)
Tristan Gingold
2022-03-04
1
-0
/
+7
*
vhdl: recognize ror/rol from ieee.numeric_std. For #1909
Tristan Gingold
2021-11-11
1
-0
/
+4
*
vhdl: Iir_Kind_Foreign_Module is now a library unit
Tristan Gingold
2021-11-09
1
-29
/
+30
*
vhdl: parse PSL inherit spec. For #1899
Tristan Gingold
2021-11-04
1
-6
/
+16
*
vhdl: also warns on unused enumeration literal
Tristan Gingold
2021-11-01
1
-0
/
+2
*
Add parsing of case? statement and simple test.
Brian Padalino
2021-09-24
1
-0
/
+7
*
trans-chap9.adb: handle async_abort, sync_abort. Fix #1654
Tristan Gingold
2021-08-30
1
-0
/
+16
*
vhdl and psl: parse sync_abort and async_abort. For #1654
Tristan Gingold
2021-08-30
1
-0
/
+7
*
vhdl: remove iir_kind_anonymous_signal_declaration (now unused)
Tristan Gingold
2021-08-24
1
-26
/
+0
*
vhdl: introduce iir_kind_association_element_by_name
Tristan Gingold
2021-08-06
1
-0
/
+11
*
vhdl-sem_expr.adb: build element subtype for aggregate when possible.
Tristan Gingold
2021-08-03
1
-2
/
+2
*
adjust previous commit (no identifier in Psl_Default_Clock)
Tristan Gingold
2021-07-01
1
-2
/
+1
*
vhdl-nodes: remove Identifier from Psl_Default_Clock
Tristan Gingold
2021-06-30
1
-3
/
+0
*
vhdl: handle mod/rem for physical. Fix #1810
Tristan Gingold
2021-06-30
1
-0
/
+2
*
vhdl-nodes: do not reset free hooks on initialization
Tristan Gingold
2021-06-26
1
-0
/
+2
*
vhdl-nodes.ads: use pnodes layout for Number_Base_Type
Tristan Gingold
2021-06-18
1
-1
/
+8
*
vhdl: remove unused Get/Set_Alias_Declaration
Tristan Gingold
2021-05-16
1
-14
/
+0
*
vhdl: add Iir_Kind_Foreign_Module
Tristan Gingold
2021-04-05
1
-0
/
+31
*
synth: handle pow and arctan from ieee.math_real. Fix #1665
Tristan Gingold
2021-02-27
1
-0
/
+2
*
vhdl-nodes.ads: add a comment
Tristan Gingold
2021-02-27
1
-0
/
+2
*
vhdl-nodes.ads: reorder fields of block_configuration to match grammar
Tristan Gingold
2021-02-20
1
-6
/
+6
*
Add support for PSL onehot/onehot0 functions (#1633)
T. Meissner
2021-02-09
1
-1
/
+14
*
vhdl: recognize to_stdlogicvector. For #1628
Tristan Gingold
2021-02-04
1
-0
/
+1
*
update license headers
umarcor
2021-01-14
1
-11
/
+9
*
Typo fixes in Ada code.
Patrick Lehmann
2021-01-10
1
-45
/
+45
*
vhdl: fix reprint of vhdl08 array element constraints.
Tristan Gingold
2021-01-05
1
-0
/
+17
*
vhdl: recognize ieee.numeric_std_unsigned. For #1572
Tristan Gingold
2021-01-01
1
-0
/
+3
*
Rework initialization and finalization.
Tristan Gingold
2020-12-30
1
-1
/
+4
*
vhdl: handle locally static attributes on entity/architecture/configurations
Tristan Gingold
2020-12-08
1
-0
/
+12
*
vhdl: recognize logica vec/log and log/vec operators. For #1520
Tristan Gingold
2020-12-03
1
-0
/
+14
*
vhdl: analyze subprogram instantiations. WIP. For #1470
Tristan Gingold
2020-09-26
1
-2
/
+8
*
vhdl: parse subprogram instantiations. For #1470
Tristan Gingold
2020-09-24
1
-0
/
+30
*
vhdl: recognize find_leftmost/find_rightmost. For #1460
Tristan Gingold
2020-09-16
1
-0
/
+6
*
vhdl: recognize reduce operations from numeric_std.
Tristan Gingold
2020-09-14
1
-0
/
+14
*
vhdl: recognize more operators for std_logic_unsigned/signed.
Tristan Gingold
2020-08-07
1
-0
/
+36
*
vhdl: recognize more std_logic_arith operators.
Tristan Gingold
2020-08-07
1
-0
/
+15
*
vhdl: parse and analyze force/release signal assignment statements.
Tristan Gingold
2020-08-01
1
-0
/
+44
*
vhdl: adjust hanlding of guard signals for translate.
Tristan Gingold
2020-07-25
1
-0
/
+2
*
translate: improve support of unbounded records and arrays.
Tristan Gingold
2020-07-25
1
-0
/
+3
*
vhdl: replace base_type with parent_type in nodes
Tristan Gingold
2020-07-22
1
-38
/
+13
*
vhdl: fix ownership for recors subtypes.
Tristan Gingold
2020-07-18
1
-3
/
+7
*
vhdl-nodes: reduce size of Iterator_Declaration.
Tristan Gingold
2020-07-01
1
-3
/
+3
*
vhdl-nodes: make Subtype_Indication Maybe_Ref. For #641
Tristan Gingold
2020-06-30
1
-3
/
+14
*
vhdl-nodes: add Open_Flag to all generic interfaces.
Tristan Gingold
2020-06-26
1
-3
/
+10
*
synth: handle std_logic_signed.conv_integer. For ghdl/ghdl-yosys-plugin#126
Tristan Gingold
2020-06-19
1
-0
/
+2
*
vhdl: decode to_x01 (from ieee.std_logic_1164)
Tristan Gingold
2020-06-19
1
-0
/
+21
*
vhdl: create default configuration for a vunit. Fix #1372
Tristan Gingold
2020-06-15
1
-4
/
+10
*
vhdl: analyze and synth concurrent statements in vunit. Fix #1366
Tristan Gingold
2020-06-12
1
-0
/
+5
*
Synthesis of PSL prev function.
Tristan Gingold
2020-06-02
1
-7
/
+11
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