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vhdl-ieee-std_logic_1164.adb
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*
update license headers
umarcor
2021-01-14
1
-11
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+9
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vhdl: recognize logica vec/log and log/vec operators. For #1520
Tristan Gingold
2020-12-03
1
-0
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+82
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*
vhdl: replace base_type with parent_type in nodes
Tristan Gingold
2020-07-22
1
-0
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+1
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Only for subtype definition and remove base_type in type definitions. Allows to better track the addition of contraints.
*
vhdl: decode to_x01 (from ieee.std_logic_1164)
Tristan Gingold
2020-06-19
1
-0
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+7
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synth: handle reduction operators. Fix #1342
Tristan Gingold
2020-05-27
1
-4
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+10
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synth-oper: recognize more operations from std_logic_arith.
Tristan Gingold
2020-04-12
1
-0
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+2
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vhdl: recognize conversion functions from std_logic_1164
Tristan Gingold
2020-02-18
1
-0
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+43
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synth: handle some rotation and shifts. Fix #1077
Tristan Gingold
2020-01-30
1
-0
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+44
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vhdl: recognize ieee.std_logic_1164.is_x.
Tristan Gingold
2019-12-24
1
-0
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+6
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vhdl-ieee-std_logic_1164: minor simplification.
Tristan Gingold
2019-11-06
1
-21
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+8
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synth: handle edge operators in synth_predefined_function_call.
Tristan Gingold
2019-11-06
1
-3
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+4
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vhdl: recognize rising_edge/falling_edge.
Tristan Gingold
2019-11-06
1
-6
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+12
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vhdl: recognize to_bitvector.
Tristan Gingold
2019-10-07
1
-81
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+72
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vhdl: recognize 1164 condition operator, handle in synth.
Tristan Gingold
2019-08-30
1
-5
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+15
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initial support for reduce and/or (#900)
Pepijn de Vos
2019-08-20
1
-5
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+18
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vhdl: extract vhdl.errors from errorout.
Tristan Gingold
2019-05-08
1
-1
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+1
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*
vhdl: move ieee packages to vhdl children.
Tristan Gingold
2019-05-05
1
-0
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+319
