iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	synth: fix handling of subtype indication in object aliases for vhdl 2008.	Tristan Gingold	2020-03-29	1	-1/+4
\| \| \| \|	Fix #1175
*	synth: avoid crash on bad elaboration order.	Tristan Gingold	2020-03-09	1	-1/+3
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*	synth: handle deferred constants. Fix #1096	Tristan Gingold	2020-01-16	1	-0/+3
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*	synth: support multiple synthesis.	Tristan Gingold	2019-12-02	1	-0/+28
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*	synth: file support (WIP).	Tristan Gingold	2019-11-12	1	-1/+2
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*	synth: initial support for file types. For #1004	Tristan Gingold	2019-11-11	1	-27/+33
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*	synth: initial support of access type. For #1004	Tristan Gingold	2019-11-11	1	-0/+4
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*	vhdl: allow attributes in vunit declarations.	Tristan Gingold	2019-10-30	1	-1/+3
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*	synth: handle concurrent signal assignment in vunits.	Tristan Gingold	2019-10-25	1	-0/+2
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*	vhdl-annotations: extract annotate_concurrent_statement.	Tristan Gingold	2019-10-25	1	-47/+53
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*	vhdl-annotations: minor renaming.	Tristan Gingold	2019-10-25	1	-8/+8
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*	vhdl-annotations: handle some declarations in vunits.	Tristan Gingold	2019-10-23	1	-0/+6
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*	vhdl: handle cover and restrict within vunit.	Tristan Gingold	2019-10-15	1	-1/+3
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*	vhdl-annotations: handle list of record elements declaration.	Tristan Gingold	2019-10-13	1	-2/+4
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*	synth: add support for concurrent procedure calls. Fix #969	Tristan Gingold	2019-10-07	1	-1/+2
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*	synth: handle record subtypes.	Tristan Gingold	2019-09-19	1	-5/+8
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*	vhdl-annotations: ignore conditional variable assignment.	Tristan Gingold	2019-08-30	1	-1/+2
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*	vhdl-annotate: handle shared anonymous subtype in interfaces.	Tristan Gingold	2019-08-30	1	-1/+4
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*	synth: add support for record types.	Tristan Gingold	2019-08-29	1	-0/+4
\| \| \| \|	(WIP: need to fix regression of stmt01).
*	synth: support sequential conditional signal assignment.	Tristan Gingold	2019-08-27	1	-0/+1
\| \| \| \|	Fix tgingold/ghdlsynth-beta#40
*	vhdl: handle assume in verification units.	Tristan Gingold	2019-08-20	1	-1/+2
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*	synth: handle verification units.	Tristan Gingold	2019-08-20	1	-1/+29
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*	Add support for PSL assumptions, used in formal verification (#880)	Pepijn de Vos	2019-08-07	1	-1/+2
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code
*	synth: improve support of vhdl08. Fix #882	Tristan Gingold	2019-08-05	1	-1/+9
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*	synth: unconstrained arrays.	Tristan Gingold	2019-07-28	1	-0/+3
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*	synth: preliminary support of dynamic indexing.	Tristan Gingold	2019-07-28	1	-45/+66
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*	vhdl annotations: fix annotation of type in interface list.	Tristan Gingold	2019-07-24	1	-0/+1
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*	synth: initial support for for-generate statement.	Tristan Gingold	2019-07-20	1	-5/+8
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*	synth: do not crash on use of std_logic_1164 2008.	Tristan Gingold	2019-07-10	1	-10/+4
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*	vhdl-annotations: partial revert of previous patch for	Tristan Gingold	2019-07-04	1	-0/+10
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*	vhdl: rename Cover_Statement to Cover_Directive.	Tristan Gingold	2019-07-04	1	-1/+1
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*	vhdl: parse and analyze restrict directive.	Tristan Gingold	2019-07-04	1	-1/+2
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*	synth: handle vhdl2008 std_logic_1164, handle anonymous_signal.	Tristan Gingold	2019-07-04	1	-2/+2
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*	vhdl: translate anonymous_signal_declaration.	Tristan Gingold	2019-07-03	1	-0/+2
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*	synth: handle concurrent assertions.	Tristan Gingold	2019-07-02	1	-1/+2
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*	vhdl: move annotations from simul to vhdl.	Tristan Gingold	2019-06-29	1	-0/+1315