index
:
iCE40/ghdl
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
src
/
vhdl
/
simulate
Commit message (
Collapse
)
Author
Age
Files
Lines
...
*
simul: support nested packages.
Tristan Gingold
2017-12-04
2
-58
/
+71
|
*
simul: WIP for nested packages.
Tristan Gingold
2017-12-04
2
-3
/
+7
|
*
simul: add iir_value_instance, remove package_instances.
Tristan Gingold
2017-12-03
8
-35
/
+81
|
*
simul: Remove scope_type (unused).
Tristan Gingold
2017-12-03
4
-186
/
+14
|
*
simul: add global_info.
Tristan Gingold
2017-12-03
6
-63
/
+77
|
*
simul: refactoring: scope is now the corresponding sim_info.
Tristan Gingold
2017-12-03
8
-112
/
+119
|
*
Create the simul.ads package (for a namespace).
Tristan Gingold
2017-11-24
23
-77
/
+97
|
*
simulation: refactoring (move block_instance to iir_values).
Tristan Gingold
2017-11-24
11
-117
/
+113
|
*
Annotations: minor reformating.
Tristan Gingold
2017-11-19
2
-24
/
+15
|
*
ghdl_simul: handle obsoleted and optionnal package body.
Tristan Gingold
2017-11-18
1
-2
/
+14
|
*
ghdl_simul: use target bounds for variable assignment of an aggregate.
Tristan Gingold
2017-11-18
1
-3
/
+1
|
*
ghdl_simul: fix crash in elaboration.
Tristan Gingold
2017-11-18
1
-10
/
+7
|
*
simulate: add per signal id.
Tristan Gingold
2017-11-16
3
-2
/
+20
|
*
simulate: add port map.
Tristan Gingold
2017-11-16
3
-16
/
+29
|
*
simulate: add extra_slot.
Tristan Gingold
2017-11-16
2
-7
/
+22
|
*
list: update simulator.
Tristan Gingold
2017-11-11
3
-30
/
+31
|
*
Update simulate.
Tristan Gingold
2017-11-08
7
-79
/
+67
|
*
simulate: update (and revive).
Tristan Gingold
2017-10-24
6
-33
/
+87
|
*
ghdl_simul: also renames conversion.
Tristan Gingold
2017-09-13
3
-9
/
+27
|
*
Fix build error for ghdlsynth.
Tristan Gingold
2017-05-09
1
-1
/
+1
|
|
|
|
For #344
*
simulate: reorder block list, support Concurrent_Simple_Signal_Assignment
Tristan Gingold
2017-01-31
4
-25
/
+60
|
*
Fix ghdlsimul build.
Tristan Gingold
2017-01-31
2
-4
/
+5
|
*
ownership: fix ghdlsimul
Tristan Gingold
2016-12-12
4
-29
/
+56
|
*
simulation: remove sim_be after previous code factorization.
Tristan Gingold
2016-10-15
5
-199
/
+61
|
*
Rework AST to setup ownership and reference policy.
Tristan Gingold
2016-10-11
2
-4
/
+2
|
|
|
|
Check it with nodes_gc.
*
Rewrite most of error and warning messages.
Tristan Gingold
2016-08-02
2
-13
/
+14
|
*
Rewrite error messages.
Tristan Gingold
2016-08-02
1
-4
/
+3
|
*
Rewrite scan error messages: use formatting.
Tristan Gingold
2016-08-02
2
-9
/
+10
|
*
Rework warnings to have a uniq tag per warning.
Tristan Gingold
2016-08-01
1
-1
/
+2
|
*
Fix indentation and English mistakes.
Tristan Gingold
2016-07-05
1
-3
/
+3
|
*
simulate/execution: uses grt.strings
Tristan Gingold
2016-06-28
1
-5
/
+6
|
*
simulation: remove unused kind_range.
Tristan Gingold
2016-03-29
2
-9
/
+1
|
*
simulation: reuse Mode_Signal_Type from grt.types.
Tristan Gingold
2016-03-10
5
-72
/
+76
|
*
elaboration: use std_time to represent time in signal table.
Tristan Gingold
2016-03-10
3
-9
/
+9
|
*
simulation: add block id.
Tristan Gingold
2016-03-10
3
-1
/
+13
|
*
simul debugger: display packages and configuration.
Tristan Gingold
2016-03-10
1
-2
/
+12
|
*
Refactoring in simulate in order to link with ortho.
Tristan Gingold
2016-02-20
12
-1213
/
+1206
|
*
simul debugger: add info instances
Tristan Gingold
2016-02-17
2
-3
/
+46
|
*
simul: fix local protected object, boolean for-generate loop
Tristan Gingold
2016-02-14
3
-38
/
+51
|
*
simul debugger: handle more concurrent statements.
Tristan Gingold
2016-02-14
1
-0
/
+50
|
*
simul: more fixes for std_ulogic.
Tristan Gingold
2016-02-14
2
-17
/
+21
|
*
psl: cover directive works on a sequence, not on a property.
Tristan Gingold
2016-02-14
2
-2
/
+48
|
*
simul: preliminary work to support PSL.
Tristan Gingold
2016-02-14
7
-105
/
+323
|
*
simul: return the exit status set by std.env
Tristan Gingold
2016-02-14
1
-2
/
+4
|
*
simul: check for no unconstrained port/generic of top-level entity.
Tristan Gingold
2016-02-14
2
-1
/
+30
|
*
simul: make delayed signal elaborated.
Tristan Gingold
2016-02-10
1
-0
/
+1
|
*
simul: add support of e8.
Tristan Gingold
2016-02-10
9
-170
/
+205
|
*
simul: handle generic override.
Tristan Gingold
2016-02-10
1
-0
/
+99
|
*
simul: handle slice in individual association for subprograms.
Tristan Gingold
2016-02-10
1
-0
/
+11
|
*
simul: fix type conversion to unconstrained array.
Tristan Gingold
2016-02-10
1
-14
/
+35
|
[prev]
[next]