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author | Tristan Gingold <tgingold@free.fr> | 2016-02-15 19:56:28 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2016-02-17 21:04:45 +0100 |
commit | 10fb178950f03784ef9316bfc70570b644cc2855 (patch) | |
tree | 0f5cd7b160ccce746a4a871f6a6b340ff303cba3 /src/vhdl/simulate | |
parent | 228c201e45fd56cb3a32fed0abb6285a95fa9c91 (diff) | |
download | ghdl-10fb178950f03784ef9316bfc70570b644cc2855.tar.gz ghdl-10fb178950f03784ef9316bfc70570b644cc2855.tar.bz2 ghdl-10fb178950f03784ef9316bfc70570b644cc2855.zip |
simul debugger: add info instances
Diffstat (limited to 'src/vhdl/simulate')
-rw-r--r-- | src/vhdl/simulate/debugger.adb | 45 | ||||
-rw-r--r-- | src/vhdl/simulate/simulation.adb | 4 |
2 files changed, 46 insertions, 3 deletions
diff --git a/src/vhdl/simulate/debugger.adb b/src/vhdl/simulate/debugger.adb index 9b9b5ae42..4ff7e4488 100644 --- a/src/vhdl/simulate/debugger.adb +++ b/src/vhdl/simulate/debugger.adb @@ -1259,6 +1259,43 @@ package body Debugger is end if; end Info_Tree_Proc; + procedure Info_Instances_Proc (Line : String) + is + pragma Unreferenced (Line); + procedure Disp_Instances (Inst : Block_Instance_Acc) + is + Child : Block_Instance_Acc; + begin + case Get_Kind (Inst.Label) is + when Iir_Kind_Architecture_Body => + Disp_Instances_Tree_Name (Inst); + when others => + null; + end case; + + Child := Inst.Children; + while Child /= null loop + if Get_Kind (Child.Label) not in Iir_Kinds_Process_Statement then + Disp_Instances (Child); + end if; + Child := Child.Brother; + end loop; + + end Disp_Instances; + begin + if Top_Instance = null then + Put_Line ("design not yet fully elaborated"); + return; + end if; + for I in Package_Instances'Range loop + if Package_Instances (I) /= null then + Put (Get_Instance_Local_Name (Package_Instances (I))); + Put_Line (" [package]"); + end if; + end loop; + Disp_Instances (Top_Instance); + end Info_Instances_Proc; + procedure Info_Params_Proc (Line : String) is pragma Unreferenced (Line); @@ -1793,10 +1830,16 @@ package body Debugger is end loop; end Cont_Proc; + Menu_Info_Instances : aliased Menu_Entry := + (Kind => Menu_Command, + Name => new String'("instances"), + Next => null, + Proc => Info_Instances_Proc'Access); + Menu_Info_Psl : aliased Menu_Entry := (Kind => Menu_Command, Name => new String'("psl"), - Next => null, + Next => Menu_Info_Instances'Access, Proc => Info_PSL_Proc'Access); Menu_Info_Stats : aliased Menu_Entry := diff --git a/src/vhdl/simulate/simulation.adb b/src/vhdl/simulate/simulation.adb index 728e7b0cb..a3d58bcd7 100644 --- a/src/vhdl/simulate/simulation.adb +++ b/src/vhdl/simulate/simulation.adb @@ -1834,8 +1834,8 @@ package body Simulation is end loop; if In_Signals /= 0 then - Error_Msg_Elab ("top entity should not have inputs signals", Entity); - -- raise Simulation_Error; + Warning_Msg_Elab + ("top entity should not have inputs signals", Entity); end if; if Disp_Stats then |