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authorTristan Gingold <tgingold@free.fr>2016-03-07 21:10:10 +0100
committerTristan Gingold <tgingold@free.fr>2016-03-10 08:01:09 +0100
commit19cfb4951c5e3b727f894faae84193a1adf81327 (patch)
tree76bc55242a32c688f2bb406309abd2433222abfc /src/vhdl/simulate
parent2acd82b0fb925dee18536b03f592459492e98703 (diff)
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simulation: reuse Mode_Signal_Type from grt.types.
Diffstat (limited to 'src/vhdl/simulate')
-rw-r--r--src/vhdl/simulate/debugger.adb22
-rw-r--r--src/vhdl/simulate/elaboration-ams.ads1
-rw-r--r--src/vhdl/simulate/elaboration.adb58
-rw-r--r--src/vhdl/simulate/elaboration.ads25
-rw-r--r--src/vhdl/simulate/simulation-main.adb42
5 files changed, 76 insertions, 72 deletions
diff --git a/src/vhdl/simulate/debugger.adb b/src/vhdl/simulate/debugger.adb
index 5225bc0ad..058e3c480 100644
--- a/src/vhdl/simulate/debugger.adb
+++ b/src/vhdl/simulate/debugger.adb
@@ -41,6 +41,7 @@ with Execution; use Execution;
--with Simulation; use Simulation;
with Iirs_Walk; use Iirs_Walk;
with Areapools; use Areapools;
+with Grt.Types;
with Grt.Disp;
with Grt.Readline;
with Grt.Errors;
@@ -640,34 +641,37 @@ package body Debugger is
procedure Disp_Signals_Stats
is
- type Counters_Type is array (Signal_Type_Kind) of Natural;
+ use Grt.Types;
+ type Counters_Type is array (Mode_Signal_Type) of Natural;
Counters : Counters_Type := (others => 0);
+ Nbr_User_Signals : Natural := 0;
Nbr_Signal_Elements : Natural := 0;
begin
for I in Signals_Table.First .. Signals_Table.Last loop
declare
Ent : Signal_Entry renames Signals_Table.Table (I);
begin
- if Ent.Kind = User_Signal then
+ if Ent.Kind in Mode_Signal_User then
+ Nbr_User_Signals := Nbr_User_Signals + 1;
Nbr_Signal_Elements := Nbr_Signal_Elements +
Get_Nbr_Of_Scalars (Signals_Table.Table (I).Sig);
end if;
Counters (Ent.Kind) := Counters (Ent.Kind) + 1;
end;
end loop;
- Put (Integer'Image (Counters (User_Signal)));
+ Put (Integer'Image (Nbr_User_Signals));
Put_Line (" declared user signals or ports");
Put (Integer'Image (Nbr_Signal_Elements));
Put_Line (" user signals sub-elements");
- Put (Integer'Image (Counters (Implicit_Quiet)));
+ Put (Integer'Image (Counters (Mode_Quiet)));
Put_Line (" 'quiet implicit signals");
- Put (Integer'Image (Counters (Implicit_Stable)));
+ Put (Integer'Image (Counters (Mode_Stable)));
Put_Line (" 'stable implicit signals");
- Put (Integer'Image (Counters (Implicit_Delayed)));
+ Put (Integer'Image (Counters (Mode_Delayed)));
Put_Line (" 'delayed implicit signals");
- Put (Integer'Image (Counters (Implicit_Transaction)));
+ Put (Integer'Image (Counters (Mode_Transaction)));
Put_Line (" 'transaction implicit signals");
- Put (Integer'Image (Counters (Guard_Signal)));
+ Put (Integer'Image (Counters (Mode_Guard)));
Put_Line (" guard signals");
end Disp_Signals_Stats;
@@ -1544,7 +1548,7 @@ package body Debugger is
begin
Disp_Instance_Name (S.Instance, False);
Put ('.');
- if S.Kind = User_Signal then
+ if S.Kind in Grt.Types.Mode_Signal_User then
Put (Name_Table.Image (Get_Identifier (S.Decl)));
Disp_Value (S.Sig);
Disp_Value (S.Val);
diff --git a/src/vhdl/simulate/elaboration-ams.ads b/src/vhdl/simulate/elaboration-ams.ads
index 8c786969e..f4c295a97 100644
--- a/src/vhdl/simulate/elaboration-ams.ads
+++ b/src/vhdl/simulate/elaboration-ams.ads
@@ -16,7 +16,6 @@
-- Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-- 02111-1307, USA.
-with Grt.Types; use Grt.Types;
with Tables;
package Elaboration.AMS is
diff --git a/src/vhdl/simulate/elaboration.adb b/src/vhdl/simulate/elaboration.adb
index ed9a02fe6..a4919147c 100644
--- a/src/vhdl/simulate/elaboration.adb
+++ b/src/vhdl/simulate/elaboration.adb
@@ -26,7 +26,6 @@ with Libraries;
with Name_Table;
with File_Operation;
with Iir_Chains; use Iir_Chains;
-with Grt.Types; use Grt.Types;
with Elaboration.AMS; use Elaboration.AMS;
with Areapools; use Areapools;
with Grt.Errors;
@@ -164,11 +163,32 @@ package body Elaboration is
Block.Objects (Slot) := Sig;
Block.Objects (Slot + 1) := Def;
- Signals_Table.Append ((Kind => User_Signal,
- Decl => Signal,
- Sig => Sig,
- Val => Def,
- Instance => Block));
+ case Get_Kind (Signal) is
+ when Iir_Kind_Interface_Signal_Declaration =>
+ case Get_Mode (Signal) is
+ when Iir_Unknown_Mode =>
+ raise Internal_Error;
+ when Iir_Linkage_Mode =>
+ Signals_Table.Append ((Mode_Linkage,
+ Signal, Sig, Def, Block));
+ when Iir_Buffer_Mode =>
+ Signals_Table.Append ((Mode_Buffer,
+ Signal, Sig, Def, Block));
+ when Iir_Out_Mode =>
+ Signals_Table.Append ((Mode_Out,
+ Signal, Sig, Def, Block));
+ when Iir_Inout_Mode =>
+ Signals_Table.Append ((Mode_Inout,
+ Signal, Sig, Def, Block));
+ when Iir_In_Mode =>
+ Signals_Table.Append ((Mode_In,
+ Signal, Sig, Def, Block));
+ end case;
+ when Iir_Kind_Signal_Declaration =>
+ Signals_Table.Append ((Mode_Signal, Signal, Sig, Def, Block));
+ when others =>
+ Error_Kind ("elaborate_signal", Signal);
+ end case;
end Elaborate_Signal;
function Execute_Time_Attribute (Instance : Block_Instance_Acc; Attr : Iir)
@@ -188,7 +208,7 @@ package body Elaboration is
end Execute_Time_Attribute;
procedure Elaborate_Implicit_Signal
- (Instance: Block_Instance_Acc; Signal: Iir; Kind : Signal_Type_Kind)
+ (Instance: Block_Instance_Acc; Signal: Iir; Kind : Mode_Signal_Type)
is
Info : constant Sim_Info_Acc := Get_Info (Signal);
Prefix : Iir_Value_Literal_Acc;
@@ -196,7 +216,7 @@ package body Elaboration is
Sig : Iir_Value_Literal_Acc;
Init : Iir_Value_Literal_Acc;
begin
- if Kind = Implicit_Transaction then
+ if Kind = Mode_Transaction then
T := 0;
Init := Create_B1_Value (False);
else
@@ -212,24 +232,24 @@ package body Elaboration is
Prefix := Execute_Name (Instance, Get_Prefix (Signal), True);
Prefix := Unshare_Bounds (Prefix, Global_Pool'Access);
case Kind is
- when Implicit_Stable =>
- Signals_Table.Append ((Kind => Implicit_Stable,
+ when Mode_Stable =>
+ Signals_Table.Append ((Kind => Mode_Stable,
Decl => Signal,
Sig => Sig,
Val => Init,
Instance => Instance,
Time => Std_Time (T),
Prefix => Prefix));
- when Implicit_Quiet =>
- Signals_Table.Append ((Kind => Implicit_Quiet,
+ when Mode_Quiet =>
+ Signals_Table.Append ((Kind => Mode_Quiet,
Decl => Signal,
Sig => Sig,
Val => Init,
Instance => Instance,
Time => Std_Time (T),
Prefix => Prefix));
- when Implicit_Transaction =>
- Signals_Table.Append ((Kind => Implicit_Transaction,
+ when Mode_Transaction =>
+ Signals_Table.Append ((Kind => Mode_Transaction,
Decl => Signal,
Sig => Sig,
Val => Init,
@@ -294,7 +314,7 @@ package body Elaboration is
Init := Unshare (Init, Global_Pool'Access); -- Create a full copy.
Instance.Objects (Info.Slot + 1) := Init;
- Signals_Table.Append ((Kind => Implicit_Delayed,
+ Signals_Table.Append ((Kind => Mode_Delayed,
Decl => Signal,
Sig => Sig,
Val => Init,
@@ -1368,7 +1388,7 @@ package body Elaboration is
Instance.Objects (Info.Slot) := Sig;
Instance.Objects (Info.Slot + 1) := Val;
- Signals_Table.Append ((Kind => Guard_Signal,
+ Signals_Table.Append ((Kind => Mode_Guard,
Decl => Guard,
Sig => Sig,
Val => Val,
@@ -2512,11 +2532,11 @@ package body Elaboration is
when Iir_Kind_Delayed_Attribute =>
Elaborate_Delayed_Signal (Instance, Decl);
when Iir_Kind_Stable_Attribute =>
- Elaborate_Implicit_Signal (Instance, Decl, Implicit_Stable);
+ Elaborate_Implicit_Signal (Instance, Decl, Mode_Stable);
when Iir_Kind_Quiet_Attribute =>
- Elaborate_Implicit_Signal (Instance, Decl, Implicit_Quiet);
+ Elaborate_Implicit_Signal (Instance, Decl, Mode_Quiet);
when Iir_Kind_Transaction_Attribute =>
- Elaborate_Implicit_Signal (Instance, Decl, Implicit_Transaction);
+ Elaborate_Implicit_Signal (Instance, Decl, Mode_Transaction);
when Iir_Kind_Non_Object_Alias_Declaration =>
null;
diff --git a/src/vhdl/simulate/elaboration.ads b/src/vhdl/simulate/elaboration.ads
index dc7965413..f9a956128 100644
--- a/src/vhdl/simulate/elaboration.ads
+++ b/src/vhdl/simulate/elaboration.ads
@@ -21,7 +21,7 @@ with Tables;
with Types; use Types;
with Iirs; use Iirs;
with Iir_Values; use Iir_Values;
-with Grt.Types;
+with Grt.Types; use Grt.Types;
with Annotations; use Annotations;
with Areapools;
@@ -183,26 +183,23 @@ package Elaboration is
Table_Initial => 32);
-- Signals.
- -- FIXME: use Mode_Signal_Type instead ?
- type Signal_Type_Kind is
- (User_Signal,
- Implicit_Quiet, Implicit_Stable, Implicit_Delayed,
- Implicit_Transaction,
- Guard_Signal);
-
- type Signal_Entry (Kind : Signal_Type_Kind := User_Signal) is record
+
+ type Signal_Entry (Kind : Mode_Signal_Type := Mode_Signal) is record
Decl : Iir;
Sig : Iir_Value_Literal_Acc;
Val : Iir_Value_Literal_Acc;
Instance : Block_Instance_Acc;
case Kind is
- when User_Signal =>
+ when Mode_Signal_User =>
null;
- when Implicit_Quiet | Implicit_Stable | Implicit_Delayed
- | Implicit_Transaction =>
- Time : Grt.Types.Std_Time;
+ when Mode_Quiet | Mode_Stable | Mode_Delayed
+ | Mode_Transaction =>
+ Time : Std_Time;
Prefix : Iir_Value_Literal_Acc;
- when Guard_Signal =>
+ when Mode_Guard =>
+ null;
+ when Mode_Conv_In | Mode_Conv_Out | Mode_End =>
+ -- Unused.
null;
end case;
end record;
diff --git a/src/vhdl/simulate/simulation-main.adb b/src/vhdl/simulate/simulation-main.adb
index cd93165da..0faf6254c 100644
--- a/src/vhdl/simulate/simulation-main.adb
+++ b/src/vhdl/simulate/simulation-main.adb
@@ -851,7 +851,7 @@ package body Simulation.Main is
Val : Iir_Value_Literal_Acc;
Time : Std_Time;
Prefix : Iir_Value_Literal_Acc;
- Kind : Signal_Type_Kind)
+ Kind : Mode_Signal_Type)
is
procedure Register_Prefix (Pfx : Iir_Value_Literal_Acc) is
begin
@@ -872,13 +872,13 @@ package body Simulation.Main is
end Register_Prefix;
begin
case Kind is
- when Implicit_Stable =>
+ when Mode_Stable =>
Sig.Sig := Grt.Signals.Ghdl_Create_Stable_Signal
(To_Ghdl_Value_Ptr (Val.B1'Address), Time);
- when Implicit_Quiet =>
+ when Mode_Quiet =>
Sig.Sig := Grt.Signals.Ghdl_Create_Quiet_Signal
(To_Ghdl_Value_Ptr (Val.B1'Address), Time);
- when Implicit_Transaction =>
+ when Mode_Transaction =>
Sig.Sig := Grt.Signals.Ghdl_Create_Transaction_Signal
(To_Ghdl_Value_Ptr (Val.B1'Address));
when others =>
@@ -930,6 +930,7 @@ package body Simulation.Main is
-- Create a new signal, using DEFAULT as initial value.
-- Set its number.
procedure Create_User_Signal (Block: Block_Instance_Acc;
+ Mode : Mode_Signal_Type;
Signal: Iir;
Sig : Iir_Value_Literal_Acc;
Val : Iir_Value_Literal_Acc)
@@ -1024,34 +1025,14 @@ package body Simulation.Main is
end Create_Signal;
Sig_Type: constant Iir := Get_Type (Signal);
- Mode : Mode_Signal_Type;
Kind : Kind_Signal_Type;
- type Iir_Mode_To_Mode_Signal_Type is
- array (Iir_Mode) of Mode_Signal_Type;
- Iir_Mode_To_Mode_Signal : constant Iir_Mode_To_Mode_Signal_Type :=
- (Iir_Unknown_Mode => Mode_Signal,
- Iir_Linkage_Mode => Mode_Linkage,
- Iir_Buffer_Mode => Mode_Buffer,
- Iir_Out_Mode => Mode_Out,
- Iir_Inout_Mode => Mode_Inout,
- Iir_In_Mode => Mode_In);
-
type Iir_Kind_To_Kind_Signal_Type is
array (Iir_Signal_Kind) of Kind_Signal_Type;
Iir_Kind_To_Kind_Signal : constant Iir_Kind_To_Kind_Signal_Type :=
(Iir_Register_Kind => Kind_Signal_Register,
Iir_Bus_Kind => Kind_Signal_Bus);
begin
- case Get_Kind (Signal) is
- when Iir_Kind_Interface_Signal_Declaration =>
- Mode := Iir_Mode_To_Mode_Signal (Get_Mode (Signal));
- when Iir_Kind_Signal_Declaration =>
- Mode := Mode_Signal;
- when others =>
- Error_Kind ("elaborate_signal", Signal);
- end case;
-
if Get_Guarded_Signal_Flag (Signal) then
Kind := Iir_Kind_To_Kind_Signal (Get_Signal_Kind (Signal));
else
@@ -1070,15 +1051,18 @@ package body Simulation.Main is
E : Signal_Entry renames Signals_Table.Table (I);
begin
case E.Kind is
- when Guard_Signal =>
+ when Mode_Guard =>
Create_Guard_Signal (E.Instance, E.Sig, E.Val, E.Decl);
- when Implicit_Stable | Implicit_Quiet | Implicit_Transaction =>
+ when Mode_Stable | Mode_Quiet | Mode_Transaction =>
Create_Implicit_Signal
(E.Sig, E.Val, E.Time, E.Prefix, E.Kind);
- when Implicit_Delayed =>
+ when Mode_Delayed =>
Create_Delayed_Signal (E.Sig, E.Val, E.Prefix, E.Time);
- when User_Signal =>
- Create_User_Signal (E.Instance, E.Decl, E.Sig, E.Val);
+ when Mode_Signal_User =>
+ Create_User_Signal
+ (E.Instance, E.Kind, E.Decl, E.Sig, E.Val);
+ when Mode_Conv_In | Mode_Conv_Out | Mode_End =>
+ raise Internal_Error;
end case;
end;
end loop;