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path: root/src/vhdl/simulate/simul-elaboration.adb
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* simul: remove ports_map from instances (not used).Tristan Gingold2018-01-021-5/+0
* simul: Add subprogram body in frames.Tristan Gingold2017-12-211-2/+8
* simul: handle psl endpoints (and adjust issue45).Tristan Gingold2017-12-211-3/+13
* simul: create initial driver value.Tristan Gingold2017-12-211-8/+15
* simul: minor refactoring.Tristan Gingold2017-12-211-4/+2
* simul-elaboration: handle unbounded records.Tristan Gingold2017-12-111-1/+1
* simul: Check range of the result of concat operator.Tristan Gingold2017-12-111-5/+1
* simul: handle optional body for package instantiation.Tristan Gingold2017-12-071-2/+5
* simul: handle interface type.Tristan Gingold2017-12-071-2/+4
* simul: handle generic-mapped packages.Tristan Gingold2017-12-071-4/+11
* simul: handle nested package instantiation.Tristan Gingold2017-12-071-1/+2
* simul: fix execution of actual expression.Tristan Gingold2017-12-061-3/+4
* simul: remove Current_Component (unused).Tristan Gingold2017-12-061-9/+3
* simul: fix elaboration check for package.Tristan Gingold2017-12-051-1/+5
* simul: psl default clock, unaffected waveform.Tristan Gingold2017-12-051-0/+3
* simul: handle interface subprogram.Tristan Gingold2017-12-051-8/+19
* simul: handle package interface, remove iir_value_environment.Tristan Gingold2017-12-051-7/+4
* simul: handle instantiated package.Tristan Gingold2017-12-051-1/+6
* simul: add support for case generate statetement.Tristan Gingold2017-12-041-9/+43
* simul: support nested packages.Tristan Gingold2017-12-041-4/+12
* simul: WIP for nested packages.Tristan Gingold2017-12-041-1/+1
* simul: add iir_value_instance, remove package_instances.Tristan Gingold2017-12-031-20/+38
* simul: add global_info.Tristan Gingold2017-12-031-8/+7
* simul: refactoring: scope is now the corresponding sim_info.Tristan Gingold2017-12-031-3/+4
* Create the simul.ads package (for a namespace).Tristan Gingold2017-11-241-0/+2979