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* synth-expr: handle any discrete_range in aggregate choices.Tristan Gingold2019-10-151-1/+2
* synth-insts: accept architecture instantiation in synth_dependencies.Tristan Gingold2019-10-151-2/+3
* synth-inference: handle multiple connections.Tristan Gingold2019-10-141-14/+31
* synth-infere: extract clock from and tree.Tristan Gingold2019-10-141-17/+102
* netlists-dump: do not print name of anonymous parameters.Tristan Gingold2019-10-141-2/+6
* synth-infere: fix partial assignment with clock enable.Tristan Gingold2019-10-141-2/+9
* synth: handle constants for condition operator.Tristan Gingold2019-10-133-1/+20
* synth-stmts: fix thinko (need to adjust type for indexed a 1-bit array).Tristan Gingold2019-10-131-2/+5
* synth-stmts: handle const indexed array.Tristan Gingold2019-10-131-0/+5
* synth-oper: handle const array array concat.Tristan Gingold2019-10-131-16/+41
* synth-oper: add more operations (float div, less for arrays)Tristan Gingold2019-10-131-7/+39
* synth-stmts: improve support for associations in function calls.Tristan Gingold2019-10-131-19/+92
* synth-inst: minor refactoring.Tristan Gingold2019-10-131-3/+2
* synth-oper: handle unsigned unsigned mul.Tristan Gingold2019-10-131-0/+13
* synth-expr: handle integer type conversion.Tristan Gingold2019-10-131-1/+4
* synth-expr: handle range array attribute in slices.Tristan Gingold2019-10-131-42/+74
* vhdl: recognize std_logic_unsigned.conv_integer.Tristan Gingold2019-10-131-2/+5
* netlists-iterators: avoid a crash if no ports.Tristan Gingold2019-10-131-3/+1
* netlists-dump: improve output.Tristan Gingold2019-10-131-9/+28
* netlists-builders: adjust names of dyn_extract ports.Tristan Gingold2019-10-131-2/+2
* Show error on wait without condition (#976)Pepijn de Vos2019-10-131-0/+4
* add record (in)equality (#975)Pepijn de Vos2019-10-131-2/+4
* vhdl: recognize conv_integer functions from std_logic_arith.Tristan Gingold2019-10-111-1/+2
* vhdl: recognize std_logic_signed package (from synopsys).Tristan Gingold2019-10-111-1/+2
* vhdl: recognize minus from std_logic_unsignedTristan Gingold2019-10-111-1/+2
* synth: remove synth-typesTristan Gingold2019-10-104-91/+13
* netlists: add internings child package.Tristan Gingold2019-10-103-14/+61
* netlists-disp_vhdl: fix pasto on id_asr.Tristan Gingold2019-10-101-5/+5
* synth: handle constants for enum equality.Tristan Gingold2019-10-101-1/+5
* netlists: give a name to the free module.Tristan Gingold2019-10-101-2/+4
* synth: rewrite cleanup pass.Tristan Gingold2019-10-107-68/+188
* synth-decls: ignore use clauses.Tristan Gingold2019-10-101-0/+2
* synth-opeer: extend synth_uresizeTristan Gingold2019-10-101-1/+1
* synth-oper: handle more operators.Tristan Gingold2019-10-101-3/+6
* synth: set name on generate statements.Tristan Gingold2019-10-092-6/+16
* synth: set location on instances.Tristan Gingold2019-10-091-0/+1
* synth: use synth.source for setting location.Tristan Gingold2019-10-098-17/+34
* netlists-disp_vhdl: handle const_SB32Tristan Gingold2019-10-091-1/+2
* synth-environment: fix a thinko.Tristan Gingold2019-10-091-1/+2
* synth: improve support of procedure calls.Tristan Gingold2019-10-081-20/+25
* synth: handle read-only aliases. Fix #973Tristan Gingold2019-10-081-1/+9
* synth-context: fix encoding of discrete in aggregateTristan Gingold2019-10-081-1/+1
* synth-disp_vhdl: fix incorrect code for record of widthTristan Gingold2019-10-081-1/+3
* synth: fix mul sgn sgn width.Tristan Gingold2019-10-082-8/+9
* synth: fix incorrect order for concat.Tristan Gingold2019-10-082-3/+6
* synth-disp_vhdl: handle array/record of 1 element.Tristan Gingold2019-10-081-3/+11
* synth: handle subprograms in package body.Tristan Gingold2019-10-081-0/+5
* synth: infere_ff: handle pre-enable. Fix #964Tristan Gingold2019-10-081-23/+63
* synth: handle case statement on bit vectors.Tristan Gingold2019-10-071-0/+23
* synth: handle package bodies.Tristan Gingold2019-10-076-9/+69
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