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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-11 06:57:27 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-11 06:57:27 +0200 |
| commit | 966ffd5b0317e61f5b4e48c2e43889d055ddddcc (patch) | |
| tree | 5f925a30e8193be7cf733c5dee1dbb66fe71a568 /src/synth | |
| parent | bca8844670a1a13964f42dc4223f720c4f405939 (diff) | |
| download | ghdl-966ffd5b0317e61f5b4e48c2e43889d055ddddcc.tar.gz ghdl-966ffd5b0317e61f5b4e48c2e43889d055ddddcc.tar.bz2 ghdl-966ffd5b0317e61f5b4e48c2e43889d055ddddcc.zip | |
vhdl: recognize conv_integer functions from std_logic_arith.
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/synth-oper.adb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 6754193aa..c08a85bb3 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -1075,7 +1075,8 @@ package body Synth.Oper is end if; end if; end; - when Iir_Predefined_Ieee_Numeric_Std_Toint_Uns_Nat => + when Iir_Predefined_Ieee_Numeric_Std_Toint_Uns_Nat + | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Uns => -- UNSIGNED to Natural. declare Int_Type : constant Type_Acc := |