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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-11 06:35:48 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-11 06:35:48 +0200 |
| commit | bca8844670a1a13964f42dc4223f720c4f405939 (patch) | |
| tree | faea5ea7788fe501195c0539969f9c90aee06564 /src/synth | |
| parent | 2714a30c3753c76cda95eb994851a8be95e60ad9 (diff) | |
| download | ghdl-bca8844670a1a13964f42dc4223f720c4f405939.tar.gz ghdl-bca8844670a1a13964f42dc4223f720c4f405939.tar.bz2 ghdl-bca8844670a1a13964f42dc4223f720c4f405939.zip | |
vhdl: recognize std_logic_signed package (from synopsys).
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/synth-oper.adb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 62bc1a51e..6754193aa 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -514,7 +514,8 @@ package body Synth.Oper is when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns => -- "-" (Unsigned, Unsigned) return Synth_Dyadic_Uns (Id_Sub, True); - when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Int => + when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Int + | Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Int => -- "-" (Signed, Integer) return Synth_Dyadic_Sgn_Int (Id_Sub); when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Sgn => |